Kristof Kellens

TL;DR: In this paper, gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence.

TL;DR: In this article, the integration of vertical carbon nanotubes (CNTs) in a processing environment is evaluated, and the performance of CNT-based interconnects are compared with existing technologies at different hierarchy levels including the limitations of present deposition methods for copper and tungsten.

TL;DR: In this article, a sacrificial material deposited by CVD was used to demonstrate air gap formation in single damascene structures by UV-assisted decomposition, and the material was removed through a porous low-k cap.

TL;DR: In this article, the authors report on an aggressive scaled RMG-HKL device with tight low-V T distributions [σ(V Tsat ) ∼ 29mV (PMOS), ∼ 49mV(NMOS) at L gate ∼35nm] achieved through controlled EWF-metal alloying for NMOS, and provide an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-

TL;DR: In this paper, a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration is presented.