Showing papers by "Muhammad Mustafa Hussain published in 2013"
TL;DR: The read operation of memristor-based memories is investigated and a new technique for solving the sneak paths problem by gating the memory cell using a three-terminal memistor device is introduced.
378 citations
TL;DR: In this article, a silicon vertical nanotube (NT) architecture-based FET was proposed to increase typically low output drive currents from tunnel field effect transistors (FETs).
Abstract: To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.
99 citations
TL;DR: With increased world population and concerns about health care, it is important to develop technologies which will be integrated in a benign way to humans or garments capable of collecting and transmitting necessary real-time data.
Abstract: Silicon electronics are at the heart of today’s digital world. Silicon based micro-fabrication technology has unparalleled performance, cost, and yield advantages. However, silicon is brittle and cannot be used for many healthcare and electronic applications. Most living organs are intrinsically of irregular shapes and thus medical electronics intended for implantation on host features such as eye balls or ears need to be fl exible. [ 1 ] Therefore, exploration for a low-cost, simple solution using plastic as substrate and organic materials to fabricate fl exible electronics, like displays and sensors, is on the rise. [ 2–5 ] The basic challenges associated with fl exible electronics compared to precision silicon technology are high thermal budget process incompatibility and inherently low electron mobility. [ 6 ] These two major challenges hinder their potential to integrate high performance devices on a traditional plastic based fl exible platform. With increased world population and concerns about health care, it is important to develop technologies which will be integrated in a benign way to humans or garments capable of collecting and transmitting necessary real-time data to address issues like seizure, heart attacks, etc. [ 7 ] This means high performance silicon-based transistors are required to be implemented on fl exible platforms. Simultaneously, such systems would require ultralow power consumption sourced conveniently from the surrounding environment. Thermoelectric energy harvesters (generators or TEGs) are one of the most pragmatic options to serve as a mobile power source. [ 8 ] Some micrometer-sized TEGs are even commercially available. [ 9–11 ] A few efforts have been made to fabricate them on fl exible substrates like polymide sheet and SU-8 based polymers. [ 12–15 ] Major challenges with these materials are (i) their low melting point making them incompatible for high temperature operation; (ii) their incompatibility for thick fi lm deposition using electrochemical deposition and iii) due to low thermal conductivity ( < 1 W/mK), the temperature cannot drop across the thermocouples. Energy harvesters like TEGs have not
76 citations
TL;DR: This is the first anode material study done using the most sustainably designed microsized MFC to date, which utilizes ambient oxygen as the electron acceptor with an air cathode instead of the chemical ferricyanide and without a membrane.
Abstract: Microbial fuel cells (MFCs) are a promising alternative energy source that both generates electricity and cleans water. Fueled by liquid wastes such as wastewater or industrial wastes, the microbial fuel cell converts waste into energy. Microsized MFCs are essentially miniature energy harvesters that can be used to power on-chip electronics, lab-on-a-chip devices, and/or sensors. As MFCs are a relatively new technology, microsized MFCs are also an important rapid testing platform for the comparison and introduction of new conditions or materials into macroscale MFCs, especially nanoscale materials that have high potential for enhanced power production. Here we report a 75 μL microsized MFC on silicon using CMOS-compatible processes and employ a novel nanomaterial with exceptional electrochemical properties, multiwalled carbon nanotubes (MWCNTs), as the on-chip anode. We used this device to compare the usage of the more commonly used but highly expensive anode material gold, as well as a more inexpensive substitute, nickel. This is the first anode material study done using the most sustainably designed microsized MFC to date, which utilizes ambient oxygen as the electron acceptor with an air cathode instead of the chemical ferricyanide and without a membrane. Ferricyanide is unsustainable, as the chemical must be continuously refilled, while using oxygen, naturally found in air, makes the device mobile and is a key step in commercializing this for portable technology such as lab-on-a-chip for point-of-care diagnostics. At 880 mA/m(2) and 19 mW/m(2) the MWCNT anode outperformed the others in both current and power densities with between 6 and 20 times better performance. All devices were run for over 15 days, indicating a stable and high-endurance energy harvester already capable of producing enough power for ultra-low-power electronics and able to consistently power them over time.
73 citations
TL;DR: A generic batch process is shown to convert high performance silicon electronics into flexible and semi-transparent one while retaining its performance, process compatibility, integration density and cost.
Abstract: State-of-the art computers need high performance transistors, which consume ultra-low power resulting in longer battery lifetime. Billions of transistors are integrated neatly using matured silicon fabrication process to maintain the performance per cost advantage. In that context, low-cost mono-crystalline bulk silicon (100) based high performance transistors are considered as the heart of today's computers. One limitation is silicon's rigidity and brittleness. Here we show a generic batch process to convert high performance silicon electronics into flexible and semi-transparent one while retaining its performance, process compatibility, integration density and cost. We demonstrate high-k/metal gate stack based p-type metal oxide semiconductor field effect transistors on 4 inch silicon fabric released from bulk silicon (100) wafers with sub-threshold swing of 80 mV dec−1 and on/off ratio of near 104 within 10% device uniformity with a minimum bending radius of 5 mm and an average transmittance of ~7% in the visible spectrum.
65 citations
TL;DR: In this article, a generic process to fabricate 10,000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers was demonstrated.
Abstract: In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.
44 citations
TL;DR: In this paper, a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric was demonstrated.
Abstract: Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 cm2 and thickness: 25 μm) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections.
40 citations
TL;DR: In this article, a simple poly-(methyl methacrylate) based transfer process without post-annealing was proposed to achieve specific contact resistivity of 3.8×× 10−5 cm2 which shows 80% reduction compared to previously reported values.
Abstract: Chemical vapor deposition based graphene grown on copper foil is attractive for electronic applications owing to its reliable growth process, large area coverage, and relatively defect free nature. However, transfer of the synthesized graphene to host substrate for subsequent device fabrication is extremely sensitive and can impact ultimate performance. Although ultra-high mobility is graphene's most prominent feature, problems with high contact resistance have severely limited its true potential. Therefore, we report a simple poly-(methyl methacrylate) based transfer process without post-annealing to achieve specific contact resistivity of 3.8 × 10−5 Ω cm2 which shows 80% reduction compared to previously reported values.
34 citations
23 citations
TL;DR: In this paper, the authors report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current.
Abstract: We report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current. Through simulation and experiments, we show the effectiveness of such device architecture is capable of high performance operation compared to conventional FinFETs with comparatively higher area efficiency and lower chip latency as well as lower power consumption.
20 citations
16 Jun 2013
TL;DR: In this paper, a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metaloxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers is presented.
Abstract: This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications.
TL;DR: In this paper, an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features.
Abstract: We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.
01 Aug 2013
TL;DR: In this article, the energy reversible switching from amorphous metal based nanoelectromechanical (NEM) switch is reported, which can be used as a complementary switching element in many Nanoelectronic system applications, but its operating voltage needs to be in the realm of 1 volt or lower.
Abstract: We report observation of energy reversible switching from amorphous metal based nanoelectromechanical (NEM) switch. For ultra-low power electronics, NEM switches can be used as a complementary switching element in many nanoelectronic system applications. Its inherent zero power consumption because of mechanical detachment is an attractive feature. However, its operating voltage needs to be in the realm of 1 volt or lower. Appropriate design and lower Young's modulus can contribute achieving lower operating voltage. Therefore, we have developed amorphous metal with low Young's modulus and in this paper reporting the energy reversible switching from a laterally actuated double electrode NEM switch.
TL;DR: This work shows integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher.
Abstract: Utilization of graphene may help realize innovative low-power replacements for III–V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance–voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in ...
TL;DR: In this paper, a micrometer-sized microbial fuel cell that is able to generate nanowatt-scale power from microliters of liquids is reported, consisting of a graphene anode, an air cathode, and a polymer-based substrate platform for flexibility.
Abstract: Microbial fuel cells harvest electrical energy produced by bacteria during the natural decomposition of organic matter. We report a micrometer-sized microbial fuel cell that is able to generate nanowatt-scale power from microliters of liquids. The sustainable design is comprised of a graphene anode, an air cathode, and a polymer-based substrate platform for flexibility. The graphene layer was grown on a nickel thin film by using chemical vapor deposition at atmospheric pressure. Our demonstration provides a low-cost option to generate useful power for lab-on-chip applications and could be promising to rapidly screen and scale up microbial fuel cells for water purification without consuming excessive power (unlike other water treatment technologies).
TL;DR: In this article, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony-telluride-based thermoelectric (TE) devices on a CMOS substrate was reported, and a 2 × 2 mm2-sized integrated planar TEG was shown to harvest 0.7 μW from 21-K temperature gradient.
Abstract: This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb2Te3) thin-film-based thermoelectric (TE) devices on a CMOS substrate. The TE films are deposited on a silicon-on-insulator substrate with FinFETs (3-D multiple gate field effect transistors) via a characterized TE-film coevaporation and shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μW from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers.
TL;DR: It is demonstrated that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc.
Abstract: We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systems-on-chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.
TL;DR: In this article, a simple, low-cost, and scalable process for obtaining uniform, smooth surfaced, high quality mono-crystalline germanium (100) thin films on silicon (100).
Abstract: We demonstrate a simple, low-cost, and scalable process for obtaining uniform, smooth surfaced, high quality mono-crystalline germanium (100) thin films on silicon (100). The germanium thin films were deposited on a silicon substrate using plasma-assisted sputtering based physical vapor deposition. They were crystallized by annealing at various temperatures ranging from 700 °C to 1100 °C. We report that the best quality germanium thin films are obtained above the melting point of germanium (937 °C), thus offering a method for in-situ Czochralski process. We show well-behaved high-κ /metal gate metal–oxide–semiconductor capacitors (MOSCAPs) using this film. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
27 Apr 2013
TL;DR: In this paper, the authors show a highly manufacturable chemical vapor deposition (CVD) based simple process to grow Tungsten disulfide (WS2) directly on silicon oxide in a furnace and then its transistor action with back gated device with room temperature field effect mobility of 0.1003 cm2/V-s using the Schottky barrier contact model.
Abstract: Tungsten disulfide (WS2) is a layered transition metal dichalcogenide with a reported band gap of 1.8 eV in bulk and 1.32-1.4 eV in its thin film form. 2D atomic layers of metal dichalcogenides have shown changes in conductivity with applied electric field. This makes them an interesting option for channel material in field effect transistors (FETs). Therefore, we show a highly manufacturable chemical vapor deposition (CVD) based simple process to grow WS2 directly on silicon oxide in a furnace and then its transistor action with back gated device with room temperature field effect mobility of 0.1003 cm2/V-s using the Schottky barrier contact model. We also show the semiconducting behavior of this WS2 thin film which is more promising than thermally unstable organic materials for thin film transistor application. Our direct growth method on silicon oxide also holds interesting opportunities for macro-electronics applications.
23 Jun 2013
TL;DR: In this paper, the diffusion of tin (Sn) into industry's most widely used substrate - silicon (100) is explored to demonstrate, for the first time, a MOSFET using SiSn as channel material.
Abstract: We present a novel semiconducting alloy, Silicon-tin (SiSn), as a channel material for LSTP device applications. The diffusion of Sn into silicon has been explored to demonstrate, for the first time, a MOSFET using SiSn as channel material. The semiconducting alloy SiSn offers interesting possibilities in the realm of silicon bandgap tuning and strain engineering. Previous works have shown that Sn diffuses into silicon wafer [1], and that the SiSn alloy is semiconducting [2]. Further, recent studies have shown better MOSFET performance with GeSn as channel material, as compared to Ge [3, 4]. To complement these activities, we have explored diffusion of tin (Sn) into industry's most widely used substrate - silicon (100). The diffusion process of Sn into the silicon lattice is low cost, scalable and manufacturable. We have studied SiSn as a channel material using theoretical analysis, as well as, by MOSFET fabrication. We observe better switching performance and an order-of-magnitude reduction in Ioff of the SiSn pMOSFETs, while maintaining a similar Ion, compared to the Si devices. We also note that the Ion/Ioff ratio for pMOSFETs is improved with incorporation of Sn into the channel.
TL;DR: A generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its performance is reported in this article. But the process does not need to use any external support and it is not suitable for high power applications.
Abstract: Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 m thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).
27 Apr 2013
TL;DR: In this paper, a tungsten alloy based amorphous metal with fabrication process development of laterally actuated dual gated NEM switches with 100 nm width and 200 nm air gap is presented.
Abstract: Nanoelectromechanical (NEM) switch is an interesting ultra-low power option which can operate in the harsh environment and can be a complementary element in complex digital circuitry. Although significant advancement is happening in this field, report on ultra-low voltage (pull-in) switch which offers high switching speed and area efficiency is yet to be made. One key challenge to achieve such characteristics is to fabricate nano-scale switches with amorphous metal so the shape and dimensional integrity are maintained to achieve the desired performance. Therefore, we report a tungsten alloy based amorphous metal with fabrication process development of laterally actuated dual gated NEM switches with 100 nm width and 200 nm air-gap to result in <;5 volts of actuation voltage (Vpull-in).
TL;DR: In this article, the authors used physical vapor deposition process to verify the concept by embedding bismuth telluride and antimony-telluride through the 5 mm Plexiglas to demonstrate 10 nW of thermopower generation with a temperature gradient of 21 °C.
Abstract: Thermoelectric materials embedded through or inside exterior glass windows can act as a viable source of supplemental power in geographic locations where hot weather dominates. This thermoelectricity is generated because of the thermal difference between the high temperature outside and the relatively cold temperature inside. Using physical vapor deposition process, we experimentally verify this concept by embedding bismuth telluride and antimony telluride through the 5 mm Plexiglas to demonstrate 10 nW of thermopower generation with a temperature gradient of 21 °C. Albeit tiny at this point with non-optimized design and development, this concept can be extended for relatively large-scale power generation as an additional power supply for green building technology.
TL;DR: In this article, a generic process flow was proposed to convert traditional electronic circuits into flexible and transparent silicon fabric-based electronics, which is shown to be cost-effective and does not sacrifice performance.
Abstract: Flexible electronics is a promising field that has the potential to expand uses for both digital and analog devices. However, the new circuits have yet to match the performance, functionality, and cost-effectiveness of their conventional rigid counterparts.1–8 The application of flexible electronics in computation, communication, navigation, and other consumer functions is still far from reality. Traditionally, polymer or plastic is used as the substrate on which flexible electronics are built. There are several major challenges specific to these materials that make them unattractive from the perspective of performance and functionality. Their information processing speed is slow (the result of slow charge transport). They melt at low temperatures, which makes it difficult to subject them to traditional electronics processing. Moreover, their limited lithographic resolution makes creating small features on them a challenge. In large electronics, transfer printing can get around the low-resolution problem. But ultra-largescale integration achieved via state-of-the-art deep UV lithography is not possible with smaller electronics, which require nanowire or nanoribbon transfer. While unconventional substrates like silicon-on-insulator (SOI), ultra-thin-body SOI, and silicon (111) do not have the same problems that polymer and plastic substrates do, they are expensive. We have demonstrated a method of transforming traditional electronic circuits into flexible, transparent devices. This approach is cost-effective and does not sacrifice performance. We started with a bulk monocrystalline silicon (100) wafer, the most commonly used substrate in the electronics industry (see Figure 1). It has excellent electrical behavior: electron mobility is high in the silicon (100) plane. It is also as much as 50% less expensive than silicon (110), silicon (111), or SOI. The main challenge of our solution is the nature of the substrate. Silicon is rigid and brittle. Figure 1. A generic process flow converts silicon electronics into flexible and transparent silicon fabric-based electronics. DRIE: Deep reactive ion etching. XeF2: Xenon difluoride. CMP: Chemical mechanical polishing.
Patent•
08 Feb 2013TL;DR: In this article, an apparatus and a system for embedded thermoelectric generators are described. But the authors focus on the interface where the ambient temperatures on two sides of the interface are different.
Abstract: An apparatus and a system for embedded thermoelectric generators are disclosed. In one embodiment, the apparatus is embedded in an interface where the ambient temperatures on two sides of the interface are different. In one embodiment, the apparatus is fabricated with the interface in integrity as a unitary piece. In one embodiment, the apparatus includes a first thermoelectric material embedded through the interface. The apparatus further includes a second thermoelectric material embedded through the interface. The first thermoelectric material is electrically coupled to the second thermoelectric material. In one embodiment, the apparatus further includes an output structure coupled to the first thermoelectric material and the second thermoelectric material and configured to output a voltage.
01 Oct 2013
TL;DR: In this paper, a group IV element: tin (Sn) was integrated into silicon lattice to enhance the performance of silicon CMOS, and the electrical properties of the SiSn lattice were evaluated by performing simulations using first-principle studies, followed by experimental device fabrication and characterization.
Abstract: We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon
01 Aug 2013
TL;DR: In this article, the authors demonstrate a buried contact based novel test structure for direct contact resistivity measurement of graphene-metal interfaces and observe excellent contact resistivities ~1 μO-cm2 without any additional surface modification.
Abstract: We demonstrate a buried contact based novel test structure for direct contact resistivity measurement of graphene-metal interfaces. We also observe excellent contact resistivity ~1 μO-cm2 without any additional surface modification suggesting that the intrinsic Au-graphene contact is sufficient for achieving devices with low contact resistance. The chemical mechanical polishing less test structure and data described herein highlights an ideal methodology for systematic screening and engineering of graphene-metal contact resistivity to enable low power high speed carbon electronics.