다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Graphene based materials: Past, present and future

Molecular self-assembly is the spontaneous association of molecules under equilibrium conditions into stable, structurally well-defined aggregates joined by noncovalent bonds. Molecular self-assembly is ubiquitous in biological systems and underlies the formation of a wide variety of complex biological structures. Understanding self-assembly and the associated noncovalent interactions that connect complementary interacting molecular surfaces in biological aggregates is a central concern in structural biochemistry. Self-assembly is also emerging as a new strategy in chemical synthesis, with the potential of generating nonbiological structures with dimensions of 1 to 10(2) nanometers (with molecular weights of 10(4) to 10(10) daltons). Structures in the upper part of this range of sizes are presently inaccessible through chemical synthesis, and the ability to prepare them would open a route to structures comparable in size (and perhaps complementary in function) to those that can be prepared by microlithography and other techniques of microfabrication.

Molecular self-assembly and nanochemistry: A chemical strategy for the synthesis of nanostructures

Glacial melting in the Tibetan Plateau affects the water resources of millions of people. This study finds that—partly owing to changes in atmospheric circulations and precipitation patterns—the most intensive glacier shrinkage is in the Himalayan region, whereas glacial retreat in the Pamir Plateau region is less apparent.

Different glacier status with atmospheric circulations in Tibetan Plateau and surroundings

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Back Cover: Tin – an unlikely ally for silicon field effect transistors? (Phys. Status Solidi RRL 4/2014)

Flexible Electronics: Deterministic Integration of Out‐of‐Plane Sensor Arrays for Flexible Electronic Applications (Small 37/2016)

Stable MoS2 Field-Effect Transistors Using TiO2 Interfacial Layer at Metal/MoS2 Contact (Phys. Status Solidi A 12∕2017)

Flexible and foldable paper-substrate thermoelectric generators (TEGs) and methods for making the paper-substrate TEGs are disclosed. A method includes depositing a plurality of thermocouples in series on a paper substrate to create a paper-substrate TEG, wherein the plurality of thermocouples is deposited between two contact points of the paper-substrate TEG. The method may also include setting the power density and maximum achievable temperature gradient of the paper-substrate TEG by folding the paper-substrate TEG. A paper-substrate TEG apparatus may include a paper substrate and a plurality of thermocouples deposited in series on the paper substrate between two contact points of the paper-substrate TEG, wherein the power density and maximum achievable temperature gradient of the paper-substrate TEG is set by folding the paper-substrate TEG.

Flexible and foldable paper-substrate thermoelectric generator (teg)

We report a novel method of performance enhancement (21%) in drive current via additive process induced strain technology that incorporates both a stressor contact etch stop layer (sCESL) and a stressor spacer in short channel (Lg=30nm) band-edge (Vt = 0.3V @ EOT = 1.1nm) high-k/metal gate nMOSFETs. This demonstration also illustrates compatibility and effectiveness of strain engineering with short channel high-k/metal gate band edge devices. A blanket tensile film results in a compressive spacer that translates tensile stress in the local channel area improving nMOS drive current. Introduction: Aggressive scaling of Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) technology requires a high drive current to increase circuit speed. Mobility enhancement by substrate engineering or process induced strain gives high source injection velocity into the quasi-ballistic transport channel [1, 2]. From the 65nm node, introduction of SiGe and/or stressor nitride in Contact Etch Stop Liner (CESL) for pMOS and nMOS performance enhancement, respectively was established as a mature technology [3, 4]. However, continued scaling of the device structure and introduction of highk/metal gate devices from 45nm node requires development of new scaled down stressor and/or transforming passive components of the MOSFET devices (example: spacer, ILD, etc.) into stressor layers. To this end, we report using stressor Si3N4 as spacer film along with conventional sCESL for performance enhancement in short Lg band-edge high-k/metal gate nMOSFETs. Experiment: The process flow is detailed in table 1 and the fabricated 32nm nMOSFET image is shown in Fig. 1. Hf-La based work function engineering enables band edge nMOSFET (Fig. 2) achievement of low EOT (Fig. 3). We compared a control wafer with Si3N4 (0.05GPa) spacer and CESL, a split of a tensile CESL (+1.5GPa), a split of a tensile stressor with a split of tensile sCESL plus tensile spacer. Stress of the spacer films are obtained from global stress measurement. Results: Output characteristics of the fabricated device (Fig. 4) show clear trend of increased output current for additive process induced strain technology. Specifically, Ion-Ioff for Lg = 60nm gate devices also show around 21% increment in Ion at Ioff = 100nA/μm (Fig. 5). Transconductance is also increased by APIS (Fig. 6). The drive current enhancement plot for various gate lengths (Fig. 7) shows a clear trend of more performance gain for short channel devices. Given that the spacer width is uniform for all channel lengths, it is not surprising that the stressed channel volume fraction and therefore drive current enhancement increases for the shortest Lg devices. The percentage performance enhancement calculated from Id-Lg plot shows 21% increase in Ion values between control and APIS for nMOSFET at Lg=100nm. Comparing with uniaxial longitudinal tensile stress plot for Si (100) nMOSFET shows that ~600MPa of uniaxial stress can be generated by the stressor spacers [5]. To differentiate whether RS/D reduction is contributing in the drive current enhancement, we measured the RS/D for nMOSFETs with and without APIS and found there is no difference. Therefore, we can exclude RS/D reduction contribution for enhanced drive current in the stressor spacer devices. The performance gain with stressor spacer may originate from the enhanced carrier mobility (Fig. 8) due to the local stretching of the channel region (Fig. 9a). Another hypothesis is because of compressively stressed spacer for nMOSFET device, during the S/D activation anneal poly-Si gate cap evolves tensile stress in the vertical direction which ultimately results in lateral tension in the channel region (Fig. 9b). To hold both of these hypotheses, it is expected that the channel length will play an important role for effective transformation of the spacer induced strain in to the channel. Fig. 3 clearly shows that the drive current is enhanced with short Lg devices. Therefore, it may be both of the effects playing important role to performance enhancement in APIS. Finally, the Positive Bias Temperature Instability (PBTI) results for various overdrive conditions clearly show no significant different in Vt shift due to the APIS technology (Fig. 10). It is understandable that substrate-strain results in biaxial strain to channel and enhances carrier mobility. However, cost, scalability, complexity such as low defect eSiGe buffers, low thermal budget, and integration are challenging. Moreover, the hole mobility of the Si channel at high fields is not improved significantly except at the Ge or dual channel because the energy separation between light and heavy hole bands is not enough due to the quantization effect. In contrast, uniaxial strain offers similar electron mobility enhancement compared with biaxial strain, while the hole mobility improvement is more significant at high field. Therefore, additive process induced strain technology like the demonstrated stressor spacer plus sCESL induced performance enhancement offers more opportunity. Also, spacer is an integral part of a CMOSFET and for short channel devices it is in more close proximity of the channel. Thus, APIS provides more benefit. Conclusion: We demonstrate that stressor spacer (like stressor Si3N4) can be used to transfer stress into the channel for short channel devices in band-edge high-k/metal gate MOSFETs. This is an effective way to introduce spacer stress induced device performance enhancement without interrupting other device critical factors. As spacer is an integral passive component of a device, therefore, application of stressor spacer is a unique method for new sort of process induced strain engineering. At the same time, this new strain engineering capability additively correlates with conventional sCESL, thus makes APIS a useful and unique technology for short channel high-k/metal gate band edge devices. References: [1] M. Lundstrom, IEDM Tech. Dig., 2003, pp. 789–792; [2] C. Jungemann et. al., IEDM Tech. Dig., 2003, pp. 191–194; [3] M. Fischetti et. al., J. of App. Phy. 80(4), p.2234-2252 (1996); [4] F. Andrieu, IEEE Elect. Dev. Let. 26(10), p.755-757 (2005); [5] S. Suthram et. al., IEEE Elect. Dev. Let., 28 (1), p.58-61 (2007). Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -836A-7-2 pp. 836-837

Muhammad Mustafa Hussain

Papers

Back Cover: Tin – an unlikely ally for silicon field effect transistors? (Phys. Status Solidi RRL 4/2014)

Flexible Electronics: Deterministic Integration of Out‐of‐Plane Sensor Arrays for Flexible Electronic Applications (Small 37/2016)

Stable MoS2 Field-Effect Transistors Using TiO2 Interfacial Layer at Metal/MoS2 Contact (Phys. Status Solidi A 12∕2017)

Flexible and foldable paper-substrate thermoelectric generator (teg)

Additive Process Induced Strain (APIS) Technology for L g = 30nm Band-Edge High-k/Metal Gate nMOSFET