Showing papers by "Robert A. Reed published in 2007"

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

Abstract: The effects of heavy ion energy and nuclear interactions on the single-event upset (SEU) and single-event latchup (SEL) response of commercial and radiation-hardened CMOS ICs are explored. Above the threshold LET for direct ionization-induced upsets, little difference is observed in single-event upset and latchup cross sections measured using low versus high energy heavy ions. However, significant differences between low- and high-energy heavy ion test results are observed below the threshold LET for single-node direct ionization-induced upsets. The data suggest that secondary particles produced by nuclear interactions play a role in determining the SEU and SEL hardness of integrated circuits, especially at low LET. The role of nuclear interactions and implications for radiation hardness assurance and rate prediction are discussed.

Impact of Ion Energy and Species on Single Event Effects Analysis

Abstract: Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASA's MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process.

Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

Abstract: Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

Abstract: A radiation-hardened-by-design phase-locked loop (PLL)-designed and fabricated in 130 nm CMOS-is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs by more than two orders of magnitude as measured by the number of erroneous PLL clock pulses following a single-event. Additionally, SEU mapping indicates a 99% reduction in the vulnerable area of the radiation-hardened-by-design (RHBD) charge pump over a conventional design. Furthermore, the TPA experiments highlight the importance of the voltage-controlled oscillator in the overall SET response of the PLL implementing the RHBD charge pump.

Monte-Carlo Based On-Orbit Single Event Upset Rate Prediction for a Radiation Hardened by Design Latch

Abstract: Heavy ion cross section data taken from a hardened-by-design circuit are presented which deviate from the traditional single sensitive volume or classical rectangular parallelepiped model of single event upset. TCAD and SPICE analysis demonstrate a SEU mechanism dominated by multiple node charge collection. Monte Carlo simulation is used to model the response and predict an on-orbit error rate.

Application of RADSAFE to Model the Single Event Upset Response of a 0.25 $\mu$ m CMOS SRAM

Abstract: The RADSAFE simulation framework is described and applied to model SEU in a 0.25 mum CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs

Abstract: We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

Predicting Thermal Neutron-Induced Soft Errors in Static Memories Using TCAD and Physics-Based Monte Carlo Simulation Tools

Abstract: A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results

A Generalized SiGe HBT Single-Event Effects Model for On-Orbit Event Rate Calculations

Abstract: This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions.

Physical mechanisms of single-event effects in advanced microelectronics

Abstract: The single-event error rate in advanced semiconductor technologies can be estimated more accurately than conventional methods by using simulation based on accurate descriptions of a large number of individual particle interactions. The results can be used to select the ion types and energies for accelerator testing and to identify situations in which nuclear reactions will contribute to the error rate.

The Application of RHBD to n-MOSFETs Intended for Use in Cryogenic-Temperature Radiation Environments

Abstract: Proton and X-ray irradiation effects are investigated in 0.35 m conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 mum pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall.

The Effects of Angle of Incidence and Temperature on Latchup in 65 nm Technology

Abstract: Single event latchup (SEL) in a 65 nm CMOS technology is examined with respect to strike angle of incidence and variations in device temperature. A significant difference in device sensitivity is observed with a change in the orientation of grazing angle strikes. The impact of an extremely high aspect ratio sensitive volume on SEL rate is discussed. It is suggested that SEL experiments should be conducted at various lateral orientations when near-grazing beam angles are tested.

3-D Simulation of SEU Hardening of SiGe HBTs Using Shared Dummy Collector

Abstract: This paper presents a SEU hardening approach that uses a dummy collector to reduce charge collection in the main transistor. The dummy collector is obtained using the silicon space between adjacent HBTs. It is obtained without any process modification or area penalty. The simulations are performed for normal and angled strikes. The hardened device shows significant reduction in charge collection due to sharing of diffusive charge collection by the dummy collector. Multiple HBT arrays of regular and hardened HBT are simulated to study the simultaneous charge collection in multiple HBTs. With hardening, charge collection in multiple devices is suppressed considerably for normal and angled strikes as the shared dummy collector collects a large amount of charge.

Applications of heavy ion microprobe for single event effects analysis

Abstract: The motion of ionizing-radiation-induced rogue charge carriers in a semiconductor can create unwanted voltage and current conditions within a microelectronic circuit. If sufficient unwanted charge or current occurs on a sensitive node, a variety of single event effects (SEEs) can occur with consequences ranging from trivial to catastrophic. This paper describes the application of heavy ion microprobes to assist with calibration and validation of SEE modeling approaches.

Comparison of Measured Dark Current Distributions With Calculated Damage Energy Distributions in HgCdTe

Abstract: This paper presents a combined Monte Carlo and analytic approach to the calculation of the pixel-to-pixel distribution of proton-induced damage in a HgCdTe sensor array and compares the results to measured dark current distributions after damage by 63 MeV protons. The moments of the Coulombic, nuclear elastic and nuclear inelastic damage distributions were extracted from Monte Carlo simulations and combined to form a damage distribution using the analytic techniques first described by Marshall The calculations show that the high energy recoils from the nuclear inelastic reactions (calculated using the Monte Carlo code MCNPX) produce a pronounced skewing of the damage energy distribution. While the nuclear elastic component (also calculated using the MCNPX) contributes only a small fraction of the total nonionizing damage energy, its inclusion in the shape of the damage across the array is significant. The Coulombic contribution was calculated using the Monte Carlo radiative energy desposition (MRED), a Geant4 application. The comparison with the dark current distribution strongly suggests that mechanisms which are not linearly correlated with nonionizing damage produced according to collision kinematics are responsible for the observed dark current increases. This has important implications for the process of predicting the on-orbit dark current response of the HgCdTe sensor array.

Ion beam induced charge (IBIC) studies of silicon germanium heterojunction bipolar transistors (HBTs)

Abstract: SiGe HBTs are strong candidates for space communication applications because of their resistance to total dose effects and their overall high performance. However, they seem to be sensitive to single event upsets (SEUs). These devices were designed using deep trench isolation geometry to reduce charge collection due to ion hits outside the active area. Using four electrode (base, emitter, collector, and substrate) IBIC measurements at the Sandia Nuclear Microprobe Facility, we found that the largest fraction of the induced charge occurred on the collector and on the substrate; significantly less induced charge was found on the base electrode, and practically no induced charge was detected on the emitter. These devices showed a very well defined, high charge collection area enclosed by the deep trench. There was a sudden drop of induced charge at the trench but a long tail was present outside of the active area extending several tens of microns. The charge collection mechanisms inside and outside of the deep trench will be discussed and first results of Time Resolved IBIC in SiGe HBTs will be presented.

High Energy Neutron Multiple-Bit Upset

Abstract: Neutron-induced multiple-bit upsets (MBU) in a 90 nm CMOS SRAM are examined using Monte-Carlo simulations. While the single-bit upset (SBU) cross section is nearly independent of angle, the probability of MBU increases for neutrons incident at grazing angles.

Electrostatic mechanisms responsible for device degradation in AlGaN/AlN/GaN HEMTs

Abstract: Displacement-damage induced degradation in AlGaN/AlN/GaN HEMTs with polarization charge induced 2DEGs is examined using simulations and experiments. Carrier removal in the unintentionally doped AlGaN layer changes the space charge in the structure and this changes the band bending. The band bending decreases the 2DEG density, which in turn reduces the drain current in the device. The effect of the defect energy levels on the 2DEG density is also studied. The interplay between carrier removal, mobility degradation, and the charged defects is analyzed and quantified.

Distribution of Proton-Induced Transients in Silicon Focal Plane Arrays

Abstract: Proton-induced energy deposition in a silicon P-i-N focal plane array is analyzed with Monte Carlo based simulations. These simulations include all physical processes, including events resulting from multiple particles incident on a single pixel, to describe the experimental data accurately. Post-processing of Monte Carlo simulations is done to account for the effects of pile up (multiple hits on a single pixel during one integration time) and non-radiation-induced noise in experiment. The results are compared with experimental data, and demonstrate how direct ionization dominates the cross section, yet fluctuations in dE/dx cause a broad range of energy depositions not addressed by an average LET calculation. An event rate is predicted for a full space proton flux and the dominance of direct ionization is shown and compared to computation using constant LET methods in CREME96. This comparison shows that at lower energies, CREME96 sufficiently predicts the event rate, but at higher energies a high fidelity simulation method is needed to capture the distribution.

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

Abstract: In this work we present, for the first time, experimental results confirming an increase in single event upset (SEU) susceptibility at cold temperatures using 63 MeV protons incident on liquid-nitrogen immersed 16-bit shift registers. Silicon germanium (SiGe) BiCMOS technology has the potential to be a key platform for extreme environment electronics due to its record (Si-based) cryogenic performance and built-in multi-Mrad (SiO2) total ionizing dose (TID) tolerance.

Modeling Alpha and Neutron Induced Soft Errors in Static Random Access Memories

Abstract: Experimental thermal neutron and alpha soft error test results of a 4 Mbit SRAM fabricated on a 0.25 mum process are evaluated using Vanderbilt University's RADSAFE toolkit. The capabilities of the radiation transport code are demonstrated by accurately reproducing experimental results and predicting operational soft error rates for the memory.

Traditional methods shortfall in predicting modern microelectronics behavior in space

Abstract: Technology scaling in modern day microelectronics has introduced characteristics and limitations that impacted radiation testing and modeling to the point that rendered traditional methods and practices obsolete in many cases. There is a need to rethink test methodologies, procedures and models in order to predict the true behavior of these technologies in space. In this paper we hope to highlight some of our experiences in order to encourage the development of improved test and prediction methodologies as they apply to modern microelectronics.

Measurement and Simulation of the Variation in Proton-Induced Energy Deposition in Large Silicon Diode Arrays

Abstract: The proton induced charge deposition in a well characterized silicon P-i-N focal plane array is analyzed with Monte Carlo based simulations. These simulations include all physical processes, together with pile up, to accurately describe the experimental data. Simulation results reveal important high energy events not easily detected through experiment due to low statistics. The effects of each physical mechanism on the device response is shown for a single proton energy as well as a full proton space flux.

Experimental verification of Single Event interconnect crosstalk in a 90 nm CMOS technology

Abstract: The presence of Single Event (SE) interconnect crosstalk has been demonstrated experimentally in the IBM 90 nm CMOS9SF process. Single and Two Photon pulsed laser experiments were performed to demonstrate this phenomenon. 3D mixed-mode simulations and modeling show SE interconnect crosstalk to depend on the interconnect length and on the amount of deposited charge. Simulations have been performed at the dual operating voltages used in this technology. Experimental and accompanying simulation results show this effect to increase SE susceptibility by increasing the vulnerable area and require evaluation to assure expected hardness levels.