T
T. Gow
Researcher at IBM
Publications - 5
Citations - 759
T. Gow is an academic researcher from IBM. The author has contributed to research in topics: Extreme ultraviolet lithography & Silicon on insulator. The author has an hindex of 5, co-authored 5 publications receiving 467 citations.
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Proceedings ArticleDOI
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Ruilong Xie,Pietro Montanini,Kerem Akarvardar,Neeraj Tripathi,Balasubramanian S. Pranatharthi Haran,Scott C. Johnson,Terence B. Hook,Bassem Hamieh,D. Corliss,Junli Wang,Xin Miao,John R. Sporre,Jody A. Fronheiser,Nicolas Loubet,Min Gyu Sung,Stuart A. Sieg,Shogo Mochizuki,Christopher Prindle,Soon-Cheon Seo,Andrew M. Greene,Jeffrey C. Shearer,Andre Labonte,Su Chen Fan,Lars W. Liebmann,Robin Chao,Abraham Arceo,Kisup Chung,K. Cheon,Praneet Adusumilli,H. P. Amanapu,Zhenxing Bi,Jungho Cha,H. Chen,Richard A. Conti,Rohit Galatage,Oleg Gluschenkov,Vimal Kamineni,Ki-chul Kim,Lee Choonghyun,F. Lie,Zuoguang Liu,Sanjay Mehta,Eric R. Miller,Hiroaki Niimi,Chengyu Niu,Chanro Park,D. Park,Mark Raymond,Bhagawan Sahu,Muthumanickam Sankarapandian,Shariq Siddiqui,Richard G. Southwick,Lei Sun,Charan V. V. S. Surisetty,Stan D. Tsai,S. Whang,Peng Xu,Y. Xu,C.-C. Yeh,Peter Zeitzoff,J. Zhang,James Chingwei Li,James J. Demarest,John C. Arnold,Donald F. Canaperi,Derren N. Dunn,Nelson Felix,Dinesh Gupta,Hemanth Jagannathan,S. Kanakasabapathy,Walter Kleemeier,C. Labelle,M. Mottura,P. Oldiges,Spyridon Skordas,Theodorus E. Standaert,Tenko Yamashita,Matthew E. Colburn,Myung-Hee Na,Vamsi Paruchuri,S. Lian,R. Divakaruni,T. Gow,Seng Luan Lee,Andreas Knorr,Huiming Bu,Mukesh Khare +86 more
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.
Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Proceedings ArticleDOI
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
Tenko Yamashita,Sanjay Mehta,Veeraraghavan S. Basker,Richard G. Southwick,Amit Kumar,R. Kambhampati,Rajesh Sathiyanarayanan,J. Johnson,T. Hook,Stephan A. Cohen,James Chingwei Li,Anita Madan,Z. Zhu,Leo Tai,Yiping Yao,Pavan S. Chinthamanipeta,Marinus Hopstaken,Zuoguang Liu,Darsen D. Lu,F. Chen,Shahrukh A. Khan,Donald F. Canaperi,Balasubramanian S. Pranatharthi Haran,James H. Stathis,P. Oldiges,C-H. Lin,Shreesh Narasimha,A. Bryant,William K. Henson,S. Kanakasabapathy,Kota V. R. M. Murali,T. Gow,D. McHerron,Huiming Bu,Mukesh Khare +34 more
TL;DR: In this paper, a low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes.
Proceedings ArticleDOI
10nm FINFET technology for low power and high performance applications
Dechao Guo,H. Shang,Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Theodorus E. Standaert,Dinesh Gupta,E. Alptekin,D.I. Bae,Geum-Jong Bae,D. Chanemougame,Kangguo Cheng,Jin Cho,B. Hamieh,J. G. Hong,T. Hook,Ju-Hwan Jung,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,Derrick Liu,H. Mallela,P. Montanini,M. Mottura,S. Nam,Injo Ok,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Richard G. Southwick,Jay W. Strane,Xiao Sun,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,M. Weybright,Ruilong Xie,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,W. Yang,Mukesh Khare +63 more
TL;DR: In this paper, a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm was reported in the FinFET technology on both bulk and SOI substrates.