Showing papers by "Tetsu Tanaka published in 2014"
TL;DR: In this paper, a reconfigured wafer-to-wafer 3-D integration is proposed, where many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer.
Abstract: A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.
35 citations
TL;DR: In this paper, the impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated.
Abstract: The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 °C. However, it is not enough at 400 °C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 °C.
19 citations
TL;DR: In this article, the impacts of 3D integration processes on memory retention characteristics in thinned DRAM chip were evaluated, and the retention characteristics of DRAM cell in a DRAM-chip which was face-down bonded to an interposer with underfill degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness.
Abstract: The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.
16 citations
TL;DR: In this article, the effect of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method, and a vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400°C annealing condition.
Abstract: The effect of CVD Mn oxide layer as a barrier layer to Cu diffusion for 3-D TSV was characterized. The impact of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method. Planar Mn oxide layer of 20-nm thickness formed over thermal oxide showed an excellent barrier property to Cu diffusion after annealing at 500°C, whereas the Mn oxide over P-TEOS oxide was good enough up to 400°C annealing. On the other hand, the barrier property of Mn oxide upon O3-TEOS oxide was not as good as thermal and P-TEOS oxides. The effect of a vertical Mn oxide layer as a barrier layer to Cu diffusion from Cu TSV was evaluated by C-t analysis. Vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400°C annealing condition. However, the barrier property of CVD Mn oxide layer was degraded after annealing at 500°C.
15 citations
14 citations
27 May 2014
TL;DR: In this article, surface tension-driven self-assembly and microbump bonding using NCF (nonconductive film)-covered chips with Cu/Sn-Ag microbumps for high-throughput and high-yield direct multichip-to-wafer 3D integration was demonstrated.
Abstract: We demonstrated surface tension-driven self-assembly and microbump bonding using NCF (non-conductive film)-covered chips with Cu/Sn-Ag microbumps for high-throughput and high-yield direct multichip-to-wafer 3D integration. The NCF is a promising candidate to completely fill gaps between fine-pitch microbumps, and is essential for realizing highly-reliable microbump-to-microbump interconnections. Here, by applying the self-assembly method with strong water surface tension, the NCF-covered chips were precisely aligned to hydrophilic assembly sites defined on host Si substrates in a face-down manner with alignment accuracies of approximately 1 μm. The self-assembled chips having Cu/Sn-Ag microbumps covered with NCF were thermally compressed to obtain electrical joints between the chips and substrate after the self-assembly process. The resulting daisy chains showed good electrical characteristics with contact resistance of 53 mΩ/joint.
11 citations
27 May 2014
TL;DR: In this paper, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip.
Abstract: A novel approach to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip is proposed, fabricated and tested. In this approach, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV. As-grown polymer was tested for its physical properties and mechanical properties, and was also evaluated for their role in minimizing the thermo-mechanical stress in vicinal and via-space Si. It was found that replacing the conventional SiO 2 dielectric liner (sandwiched between the via-metal and Si) with organic polymer greatly helps in suppressing the thermo-mechanical stress, and thus the keep-out zone.
11 citations
27 May 2014
TL;DR: In this paper, a self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology was proposed and demonstrated.
Abstract: In this study, we proposed and demonstrated self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology. A hydrogenated amorphous silicon (a-Si:H) was employed as a debonding layer. Known good dies (KGDs) were precisely self-assembled right side up on an electrostatic carrier wafer by surface tension of water, and then, the KGDs were fixed by applying DC voltage to the carrier. After that, the KGDs were temporarily bonded and transferred to another support glass wafer on which the a-Si:H and SOG layers were deposited. After multichip thinning, Cu-TSVs were formed on the KGDs. The resulting TSV daisy chains showed good electrical characteristics. The KGDs can be debonded with a 308-nm laser and transferred again to target interposer wafers.
9 citations
01 Jun 2014
TL;DR: In this paper, the influences of Cu contamination on 3D DRAM memory cell retention were characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs.
Abstract: The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ~ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.
9 citations
TL;DR: In this article, a 50-μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction.
Abstract: Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.
8 citations
01 Dec 2014
TL;DR: The Ni barrier layer has good blocking properties compared to a PVD barrier layer and Cu atoms not diffuse into Si substrate via the Ni layer even after annealing at 400°C.
Abstract: Effects of electro-less Ni layer as barrier/seed layers were evaluated for high reliable and low cost Cu TSVs. To electrically characterize the effectiveness of a Ni layer as barrier/seed layers for TSV application, we fabricated the trench MOS capacitor with 5µm dia. and 50µm depth TSV array. Via holes were successfully filled by Cu electro-plating by using Ni seed layer. To characterize the blocking property of the Ni layer to Cu diffusion, Cu atoms were intentionally diffused from Cu TSV by annealing at 300°C and 400°C. X-ray spectrometer (EDX) and C-t analysis results shows that Cu atoms not diffuse into t h e Si substrate via the Ni layer even after annealing at 400°C. The Ni barrier layer has good blocking properties compared to a PVD barrier layer.
27 May 2014
TL;DR: In this paper, the effects of low temperature curing adhesive on both the local bending stress and the resultant transistor characteristics for decrease in keep-out-zone (KOZ) of 3D IC were evaluated.
Abstract: Three dimensional IC (3D IC) has lots of through-Si vias (TSVs) and metal microbumps for electrical connection between stacked IC chips, and also has organic adhesives to enhance the mechanical strength of 3D IC. However, the coefficient of thermal expansion (CTE) mismatch between microbumps and organic adhesives generate the local bending stress in thinned IC chips. Therefore, Keep-Out-Zone (KOZ) for transistors must be considered in 3D IC design to eliminate characteristic fluctuations and degradations due to the local bending stress. In this study, for the first time, we evaluated the effects of low temperature curing adhesive on both the local bending stress and the resultant transistor characteristics for decrease in KOZ of 3D IC.
27 May 2014
TL;DR: A 3D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed in this article, which is implemented using die-level 3D integration and backside TSV technologies.
Abstract: A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.
20 May 2014
TL;DR: In this article, the feasibility of using Cu electroless as deposition technique in a TSV metallization process was shown. But the in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm, which is much lower than would have been needed in a conventional scheme with a PVD-cu seed.
Abstract: High aspect ratio through-silicon vias (3 µm diameter by 50 µm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ∼ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.
01 Jan 2014
TL;DR: The VCSEL was accurately positioned, successfully emitted 850-nm light, and exhibited no degradation of the I-V characteristics, and recent progress on the hybrid integration of chip-scale photonic devices with 3D/TSV technologies for optical interconnections is presented.
Abstract: A 12-channel vertical cavity surface emitting laser (VCSEL) chip was heterogeneously self-assembled to a glass interposer wafer by liquid surface tension as a driving force. The size of the VCSEL chip was 0.35 mm wide and 3 mm long. From the square dummy chips having structurally similar periphery to the VCSEL, the step structure at the chip edge was found to be significantly dependent on the alignment accuracies. From the rectangular dummy chips having the same sizes to the long VCSEL, the tiny chips were precisely self-assembled with alignment accuracies within 2 µm even when they were manually placed on water droplets provided on host Si wafers. After self-assembly of the VCSEL chip and the subsequent thermal compression, the VCSEL was accurately positioned, successfully emitted 850-nm light, and exhibited no degradation of the I–V characteristics. This paper also presents our recent progress on the hybrid integration of chip-scale photonic devices with 3D/TSV technologies for optical interconnections.
01 Dec 2014
TL;DR: In this paper, a 3D stacked multicore processor module composed of 4-layer stacked 3D multicore processors and 2-layer stack 3D cache memory chip is implemented using reconfigured multichip-on-wafer 3D integration and backside TSV technologies for the first time.
Abstract: A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.
23 Apr 2014
TL;DR: In this paper, spin-on glass (SOG) and hydrogenated amorphous silicon (a-Si:H) were used as a bonding layer and debonding layer, respectively.
Abstract: A new temporary bonding technology has been demonstrated, where both spin-on glass (SOG) and hydrogenated amorphous silicon (a-Si:H) were used as a bonding layer and as a debonding layer, respectively. Square chips were bonded to a glass wafer through the SOG layer and a-Si:H layer. The SOG bonding was capable of withstanding chip thinning and high-temperature chemical vapor deposition (CVD) processes. A XeCl excimer laser was irradiated to the a-Si:H layer through the glass wafers for debonding the chips. A novel via-last/backside-via 3D integration process using temporary SOG bonding was also proposed for advanced multichip-to-wafer 3D integration with self-assembly.
01 Jan 2014
TL;DR: The optimized ELD Cu process was conducted at room temperature on activated Ru surface, which can improve the ELD bath life time and the deposited Cu with 2,2' bipyridyl shows smoother and higher purity inside the Cu film.
Abstract: High aspect ratio through-Si vias (AR=16.7) filling has been achieved by using non-PVD seed metallization approach. We demonstrate the formation of conformal and thin electroless deposited Cu seed on Ru liner. The optimized ELD Cu process was conducted at room temperature on activated Ru surface, which can improve the ELD bath life time. The deposited Cu with 2,2′ bipyridyl shows smoother and higher purity inside the Cu film.
01 Jan 2014
TL;DR: 3D-LSI stack containing diametrically highly-scaled through-silicon-vias (TSVs) with diameter 2μm as well as conventional 20 μm-width Cu-TSVs were carefully studied for thermo-mechanical stress via micro-X-ray diffraction using synchrotron radiation at Spring-8.
Abstract: 3D-LSI stack containing diametrically highly-scaled through-silicon-vias (TSVs) with diameter 2µm as well as conventional 20 µm-width Cu-TSVs were carefully studied for the thermo-mechanical stress induced by Cu-TSVs via micro-X-ray diffraction using synchrotron radiation at Spring-8. It was observed that the TSV diameter has huge impact on the magnitude of resultant thermo-mechanical stress. The 20 µm-width Cu-TSV has induced more than −1500 MPa of stress in the vicinal Si, while the 2 µm-width Cu-TSV induced less than −10 MPa of compressive stress in the surrounding Si. Therefore by decreasing the TSV diameter, one can virtually eliminate the thermo-mechanical stress induced by TSV.
15 Jul 2014
TL;DR: Sameshima et al. as mentioned in this paper introduced a highly thermoresistant temporary bonding/debonding system, where known good die (KGDs) were thinned and formed by via-last/backside-via processes.
Abstract: —This study introduces a highly thermoresistant temporary bonding/debonding system. Known Good Dies (KGDs) were bonded through SOG to a support wafer. The KGDs were thinned, and Cu-TSVs were formed by via-last/backside-via processes. These KGDs can be readily debonded from the wafer by excimer laser irradiation to the a-Si:H layer on the wafer. I. I NTRODUCTION A ND B ACKGROUND Organic temporary glues are widely employed for thin-wafer handling in 3D integration due to their excellent adhesion properties and cost-effectiveness in materials and coating processes. The only one downside is that the organic adhesives are thermally unstable at above 400°C. On the other hand, there are several options for debonding thin wafers from the organic temporary glues [1]: slide-off, thermal/mechanical/solvent release, Zone-Bond ® , and laser debonding with UV or IR sources. Any debonding systems have some drawback and advantages in throughput, reliability, and cost. SOG is well known to be inorganic or organic/inorganic hybrid materials traditionally used in semiconductor industries. In addition, compound wafers have been directly bonded through SOG without CMP [2]. Sameshima
Patent•
14 Nov 2014
TL;DR: In this article, an information acquisition program, information acquisition method and information acquisition device are provided which can complement information to be included in a document, where storage units (121, 122) store information specifying the position of specific data, and information specifying other data having a prescribed relation with the aforementioned specific data in the document.
Abstract: An information acquisition program, information acquisition method and information acquisition device are provided which can complement information to be included in a document. This information acquisition program refers to storage units (121, 122) which store information specifying the position of specific data in a document on a site, and information specifying the position of other data having a prescribed relation with the aforementioned specific data in the document, and performs processing (133) on a computer (100) to acquire the specific data using the information specifying the position of the specific data in the document on the site. Further, this information acquisition program refers to storage units (121, 122) to perform processing (134) on a computer (100) to acquire the other data using the position in the document of the other data related to the specific data and, using the acquired other data, to acquire data having a prescribed relation with the other data.
TL;DR: In this paper, a high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application.
Abstract: A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.
Patent•
14 Nov 2014
TL;DR: In this article, a data acquisition program, data acquisition method and data acquisition device are provided which can support registration of the position of data extracted from an HTML document, based on the hierarchical structure of the tags contained in the document.
Abstract: A data acquisition program, data acquisition method and data acquisition device are provided which can support registration of the position of data extracted from an HTML document. This data acquisition program executes processing (133) on a computer (100) for extracting, from a document composed in HTML, first data and second data separated by a prescribed tag or symbol therebetween. Further, the data acquisition program executes processing (134) for associating and displaying the extracted first data and second data. Further, upon detecting that the displayed first data or second data is selected, the data acquisition program executes processing (135) for specifying the position of the first data or second data in the document in terms of the hierarchical structure of the tags contained in the document. Further, the data acquisition program executes processing (135) to allow said position in the hierarchical structure to be registered.
15 Jul 2014
TL;DR: In this article, self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate and aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer.
Abstract: Self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate. Dummy chips that mimics VCSEL were aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer. The alignment accuracies were 0 and -2.0 μm in X and Y directions.
27 Nov 2014
TL;DR: In this paper, a new energy harvesting module that used the thermoelectric device (TED) by using molding technology is presented, and the output voltage per heater temperature of the TED module at 20?C ambient temperature is 8mV/K and similar to the result with the aluminium heat sink.
Abstract: This paper presents the fabrication of a new energy harvesting module that used the thermoelectric device (TED) by using molding technology. The output voltage per heater temperature of the TED module at 20 ?C ambient temperature is 8mV/K and similar to the result with the aluminium heat sink which is almost the same fin size as the TED module. The accelerated environmental tests are performed on damp heat test that is an aging test under high temperature and high humidity, cold test and highly accelerated temperature and humidity stress test (HAST) for the purpose of evaluating the electrical reliability in harsh environments. Every result of tests indicates that the TED and circuit board can be properly protected from harsh temperature and humidity by using molding technology, because the output voltage of after tested modules is reduced by less than 5%.This study presents a novel fabrication method for a high reliability TED-installed module appropriate for Machine to Machine wireless sensor networks
Patent•
14 Nov 2014
TL;DR: In this paper, the reliability of information to be described in a document and outputting it has been investigated in the context of a data verification program, where the data verification process requires the computer to execute a process (135) of outputting the information acquired as the specific information together with the specified reliability.
Abstract: Provided are a data verification program, a data verification method, and a data verification device capable of enhancing the reliability of information to be described in a document and outputting it. A data verification program causes a computer (100) to execute a process (134) of specifying, out of a plurality of sites registered as acquisition sources of specific information, the reliability of the site from which the information was acquired as the specific information based on storage content of a storage unit (120) that stores therein the reliability in association with each of the sites. The data verification program causes the computer to execute a process (135) of outputting the information acquired as the specific information together with the specified reliability.
09 Sep 2014
TL;DR: In this paper, the effect of plasma damage in TSV formation on MOSFET characteristics was investigated to discuss the new antenna rule for the 3D IC design, and the measurement results showed no significant change even after via-holes formation.
Abstract: We have investigated the effect of plasma damage in TSV formation on MOSFET characteristics to discuss the new antenna rule for the 3D IC design. An IC chip for evaluation was bonded to Si interposer with Cu/Sn microbumps at 280°C for 190 sec and thinned to 50-m thickness. Via holes through a Si substrate for TSV are formed by ICP-RIE at the backside surface of the IC chip. Diameter and number of via holes are 25 m and 1, 6, 11, and 21, respectively. These via holes interconnected the first metal which interconnect the gate metal of MOSFET fabricated on IC chip. We measured the Id-Vg characteristics of the MOSFET before and after via-holes formation. The measurement results show no significant change even after via-holes formation. It is indicated that the via-hole-etching process doesn’t affect MOSFET characteristics, because the gate capacitance of MOSFET is much smaller than parasitic capacitance of the first metal.