Journal ArticleDOI
A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator
HeungJun Jeon,Yong-Bin Kim +1 more
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TLDR
In this paper, a dynamic latched comparator with offset voltage compensation is presented, which uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage.Abstract:
A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.read more
Citations
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Journal ArticleDOI
Optimum design of a double-tail latch comparator on power, speed, offset and size
Ehsan Yaqubi,Seyed Hamid Zahiri +1 more
TL;DR: This paper presents an optimum design of a double-tail latch comparator based on transistor sizing with a great certainty to reach the best possible design due to using Hspice (as a software simulator linked with a heuristic algorithm) to achieve a low-power, high-speed, low offset and, small size comparator.
Journal ArticleDOI
A novel low offset low power CMOS dynamic comparator
TL;DR: In this paper, a fully dynamic double tail dynamic comparator was proposed to meet the necessity of low offset voltage with optimum power with relatively high speed, and the offset voltage and delay of the proposed comparator were derived.
Journal ArticleDOI
Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process
Labonnah Farzana Rahman,Mamun Bin Ibne Reaz,Chia Chieu Yin,Mohammad Alauddin Mohammad Ali,Mohammad Marufuzzaman +4 more
TL;DR: Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current.
Dissertation
Development of CMOS pixel sensors for the inner tracking system upgrade of the ALICE experiment
TL;DR: This thesis presents in detail the design and the measurement results of these AROM sensors, incorporating the optimized pixel designs and the necessary on-chip intelligence to approach the final sensor proposed for the ALICE-ITS upgrade.
Journal ArticleDOI
A 1.17-Megapixel CMOS Image Sensor With 1.5 A/D Conversions per Digital CDS Pixel Readout and Four In-Pixel Gain Steps
TL;DR: A method to reduce the pixel readout energy consumption by computing two digital correlated double-sampling (DCDS) results with three analog–digital (A/D) conversions, thereby using an average of 1.5 A/D conversions per pixel.
References
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Journal ArticleDOI
Matching properties of MOS transistors
TL;DR: In this article, the matching properties of the threshold voltage, substrate factor and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on a band-gap reference circuit.
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TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Proceedings ArticleDOI
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Journal ArticleDOI
Yield and speed optimization of a latch-type voltage sense amplifier
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.