Patent
3d semiconductor device
Zvi Or-Bach,Zeev Wurman +1 more
TLDR
In this paper, a semiconductor device comprising first layer comprising multiplicity of first transistors and second layer consisting multiplicityof second transistors is defined, and at least one function constructed by the first transistor is structure so it could be replaced by a function created by the second transistor.Abstract:
A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.read more
Citations
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Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Systems and methods for computer assisted operation
TL;DR: In this paper, an augmented reality method includes selecting an image of an object to be installed, converting the image into a 3D model, capturing a view of an environment and selecting a place to insert the 3D models, overlaying the model with the view of the environment in a mashed-up and aligned manner, and enabling user interaction with the displayed model view to update the model.
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3d floorplanning using 2d and 3d blocks
TL;DR: In this article, the authors present a methodology for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies.
Patent
Monolithic three dimensional integration of semiconductor integrated circuits
TL;DR: In this article, a three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier Vias, and metal layers to connect together the various transistors.
Patent
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
TL;DR: In this article, a 3D integrated circuit (3DIC) with a graphene shield is described, where at least a graphene layer is positioned between two adjacent tiers of the 3DIC.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Patent
Three dimensional structure memory
TL;DR: The 3Dimensional Structure (3DS) Memory (100) as mentioned in this paper is a three-dimensional structure (3D) memory that allows physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized.