Proceedings ArticleDOI
A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology
Christian Fayomi,Gordon W. Roberts,Mohamad Sawan +2 more
- Vol. 1, pp 460-463
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TLDR
Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented and a track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-toAbstract:
Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 /spl mu/m digital process are presented. A track-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail track-and-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-rail current-to-voltage converter, performs the DAC function in the second ADC topology whereas a conventional R-2R ladder is used in the first one. Successive approximation and control logic is implemented using of robust single clock phase D flip flop.read more
Citations
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Journal ArticleDOI
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
Hao-Chiao Hong,Guo-Ming Lee +1 more
TL;DR: An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic.
Journal ArticleDOI
Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs
TL;DR: It will be shown that, in spite of what commonly is assumed, although the total capacitance and the power consumption of those architectures employing attenuating capacitors seem to be smaller than conventional binary-weighted structures, the linearity requirements impose much larger unit capacitance to the structure such that the entire power consumption is larger.
Journal ArticleDOI
A time-based energy-efficient analog-to-digital converter
H.Y. Yang,R. Sarpeshkar +1 more
TL;DR: A novel current-mode algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive subranging technique is described, making it one of the most energy-efficient converters to date in the 10-12 bit precision range.
A tiq-based cmos flash a/d converter for system-on-chip applications
Kyusun Choi,Jincheol Yoo +1 more
TL;DR: The results show that the TIQ flash ADC achieves high-speed conversion, and has a small size, low-power dissipation, and low-voltage operation compared to other flash ADCs.
Journal ArticleDOI
Segmented Architecture for Successive Approximation Analog-to-Digital Converters
Mehdi Saberi,Reza Lotfi +1 more
TL;DR: The structure of a binary-weighted capacitive DAC in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce the power consumption and improve the static linearity performance.
References
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Journal ArticleDOI
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Journal ArticleDOI
An inherently linear and compact MOST-only current division technique
K. Bult,G.J.G.M. Geelen +1 more
TL;DR: In this paper, a technique that uses the same MOS transistors for both division and switching functions, eliminating resistors or capacitors, was presented, and it was shown that the current division is inherently linear.
Proceedings Article
Fractal capacitors
TL;DR: In this paper, a linear capacitance structure using fractal geometries is described, which exploits both lateral and vertical electric fields to increase the capacitance per unit area, and it is shown that capacitance boost factors in excess of ten may be possible as technology continues to scale.
Journal ArticleDOI
A 900-mV low-power /spl Delta//spl Sigma/ A/D converter with 77-dB dynamic range
TL;DR: In this paper, the design of a low-voltage and low-power /spl Delta/spl Sigma/ analog-to-digital (A/D) converter is presented.
Journal ArticleDOI
A CMOS 8-Bit High-Speed A/D Converter IC
TL;DR: In this article, a novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC.