Journal ArticleDOI
A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture
M. Miyazaki,James Kao,Anantha P. Chandrakasan +2 more
- Vol. 37, Iss: 11, pp 1545-1554
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TLDR
In this article, a theoretical model is developed to predict how dynamic power and sub-threshold power must be balanced to give an optimal V/sub DD/V/sub t/ operating point that minimizes total active power consumption.Abstract:Â
In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an optimal V/sub DD//V/sub t/ operating point that minimizes total active power consumption for different workload and operating conditions. A 175-mV multiply-accumulate test chip using a triple-well technology with tunable supply and body bias values is measured to experimentally verify the tradeoffs between the various sources of power. The test chip shows that there is an optimum V/sub DD//V/sub t/ operating point, although it differs from the theoretical limit because of excessive forward bias currents. Finally, we propose a preliminary automatic supply and body biasing architecture (ASB) that automatically configures a circuit to operate with the lowest possible active power consumption.read more
Citations
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Journal ArticleDOI
A 180-mV subthreshold FFT processor using a minimum energy design methodology
TL;DR: New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor that is designed to investigate the estimated minimum energy point.
Journal ArticleDOI
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance
Shidhartha Das,Carlos Tokunaga,Sanjay Pant,Wei-Hsiang Ma,S. Kalaiselvan,Kevin Lai,David Michael Bull,David Blaauw +7 more
TL;DR: This paper presents a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors and demonstrates SER tolerance on the RazorII processor through radiation experiments.
Journal ArticleDOI
Modeling and sizing for minimum energy operation in subthreshold circuits
TL;DR: It is shown that minimum sized devices are theoretically optimal for reducing energy, and existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.
Proceedings ArticleDOI
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
TL;DR: In this paper, the authors show how the simultaneous use of adaptive body biasing (ABB) and dynamic voltage scaling (DVS) can be used to reduce power in high-performance processors.
Journal ArticleDOI
0.5-V analog circuit techniques and their application in OTA and filter design
TL;DR: In this paper, operational transconductance amplifier (OTA) and filter design for analog circuits with very low supply voltages, down to 0.5 V, are presented. But they do not consider the effect of low-voltage analog circuits on the performance.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Journal ArticleDOI
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Journal ArticleDOI
A dynamic voltage scaled microprocessor system
TL;DR: In this article, the authors proposed a dynamic voltage scaling (DVS) strategy to achieve the highest possible energy efficiency for time-varying computational loads, which can reduce energy consumption for low computational periods while retaining peak performance when required.
Journal ArticleDOI
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
James W. Tschanz,James Kao,Siva G. Narendra,Rajendran Nair,Dimitri A. Antoniadis,Anantha P. Chandrakasan,Vivek De +6 more
TL;DR: Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each die which maximizes the die frequency subject to a power constraint as mentioned in this paper.