A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS
Xiang Gao,Eric A.M. Klumperink,Mounir Bohsali,Bram Nauta +3 more
- pp 392-393
TLDR
This paper presents a 2.2GHz clock-generation PLL that uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock and achieves a low in-band phase noise values at low power.Abstract:
A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.read more
Citations
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Journal ArticleDOI
A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
TL;DR: This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-Slope method.
Journal ArticleDOI
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing
Yi-Chieh Huang,Shen-Iuan Liu +1 more
TL;DR: A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion, but the sub-harmonically injection-locked technique, sub-sampling technique, and the multiplying delay- Locked loop (MDLL) can significantly improve the phase noise of aninteger-N PLL.
Journal ArticleDOI
A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture
TL;DR: In this paper, a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers are theoretically presented and verified with measured results.
Proceedings ArticleDOI
An injection-locked ring PLL with self-aligned injection window
Che-Fu Liang,Keng-Jan Hsiao +1 more
TL;DR: An injection-locked ring PLL (ILRPLL) architecture is proposed, using the concept of sub-sampling PLLs, where the injection window is aligned automatically without feedback adjustment, and a 432MHz ILRPLL is realized in ATV/DTV system to justify this technique.
Journal ArticleDOI
A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL
TL;DR: This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer where a PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider.
References
More filters
Journal ArticleDOI
A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.
Proceedings ArticleDOI
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
TL;DR: A digital fractional-N frequency synthesizer is presented that leverages a noise-shaping time-to-digital converter (TDC) and a simple quantization noise cancellation technique to achieve low phase noise with a wide PLL bandwidth of 500kHz.
Journal ArticleDOI
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops
TL;DR: A benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire phase-locked loops (PLL) is proposed.
Book
Frequency Synthesizer Design Handbook
TL;DR: Building Blocks for Frequency Synthesis Using Phase-Locked Loops using Sampled-Data Control Systems and Fast-Switching Frequency Synthesizer Design Considerations.