Journal ArticleDOI
A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output
S.J. Decker,D. McGrath,K. Brehmer,Charles G. Sodini +3 more
- Vol. 33, Iss: 12, pp 2081-2091
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TLDR
A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system that simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor.Abstract:
A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system. Illumination may vary over several orders of magnitude, requiring a high dynamic range imager. Dynamic range is increased 20/spl times/ using a special clocking scheme for the lateral overflow gate. This dynamic range enhancement offers improvements over previously-described techniques. It simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor. On-chip column-parallel cyclic analog-to-digital converters (ADCs) produce digital output at frame rates from 30 to 390 frames/s.read more
Citations
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Journal ArticleDOI
A Nyquist-rate pixel-level ADC for CMOS image sensors
TL;DR: A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented, ideally suited to pixel-level implementation in a CMOS image sensor.
Journal ArticleDOI
A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion
TL;DR: In this paper, a CMOS image sensor with pixel-parallel analog-to-digital (A/D) conversion fabricated with different array sizes and photodiode types in a three-metal 0.5/spl mu/m process is presented.
Journal ArticleDOI
A self-calibrating single-chip CMOS camera with logarithmic response
TL;DR: In this article, a high-dynamic-range CMOS image sensor consisting of nonintegrating, continuously working photoreceptors with logarithmic response is presented, where the nonuniformity problem caused by the device-to-device variations is greatly reduced by an implemented analog self-calibration.
Journal ArticleDOI
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors
TL;DR: A CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC that can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals.
Proceedings ArticleDOI
Trends in CMOS image sensor technology and design
TL;DR: Three trends that promise to increase CMOS image sensor system performance are presented: modifications of deep submicron CMOS processes to improve their imaging characteristics, developments that take advantage of these modified deep sub micron processes, and high frame rate sensors and applications to still and video imaging.
References
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TL;DR: In this article, the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
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A ratio-independent algorithmic analog-to-digital conversion technique
TL;DR: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology.
Book
Charge Transfer Devices
TL;DR: It is projected that charge transfer devices will rapidly find their way into certain analog delay, image sensing, and digital applications.
Journal ArticleDOI
256/spl times/256 CMOS active pixel sensor camera-on-a-chip
TL;DR: In this paper, an active pixel sensor (APS) is integrated on a CMOS chip with the timing and control circuits, and signal conditioning to enable random access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms).