Journal ArticleDOI
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications
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TLDR
A novel transceiver that consists of a single differential-amplifier and serves as both a transmitter and a receiver for transmitting signals to multipoint for on-chip high-speed networks that have big impact in chip performances is proposed.Abstract:
This paper investigates a bidirectional- and multi-drop-transmission-line interconnect for on-chip high-speed networks that have big impact in chip performances. Point-to-point on-chip transmission line interconnects have been developed and demonstrated widely. The present paper applies transmission line interconnect technologies to multipoint-to-multipoint on-chip communications. We propose the novel transceiver that consists of a single differential-amplifier and serves as both a transmitter (Tx) and a receiver (Rx) for transmitting signals to multipoint. The 5-mm-long prototype interconnect with six transceivers performs 8 Gbps signaling with power dissipation of 1.2 mW per transceiver in a 90 nm Si CMOS process. Our interconnect achieves multipoint communications with small delay and high power efficiencies.read more
Citations
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Journal ArticleDOI
A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many-Cores
TL;DR: New interconnect technologies, such as optical interconnect, wireless NoC (WiNoC), RF transmission lines (RF-I) and surface wave interconnects (SWI), are discussed, evaluated and compared.
Proceedings ArticleDOI
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
TL;DR: A novel NoC with hybrid interconnect that leverages multiple types of interconnects - specifically, conventional full-swing short-range wires for the data path, in conjunction with low-swing, multi-drop wires with long-range, ultra-low-latency communication for the flow control signals.
Journal ArticleDOI
Networks on chips: structure and design methodologies
TL;DR: Several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC are discussed and a novel bidirectional NoC (BiNoC) architecture is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.
Journal ArticleDOI
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
TL;DR: Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow and exhibits consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.
Proceedings ArticleDOI
GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs
TL;DR: This paper proposes and evaluates \textit{GLocks], a hardware-supported implementation for highly-contended locks in the context of many-core CMPs that skips the memory hierarchy to provide a non-intrusive, extremely efficient and fair lock implementation with negligible impact on energy consumption or die area.
References
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Journal ArticleDOI
Optical interconnections for VLSI systems
TL;DR: The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems, and the possibility of applying optical and electrooptical technologies to such interconnection problems is investigated.
Book
Transmission Line Design Handbook
TL;DR: In this paper, the authors present a comprehensive overview of transmission line components and discontinuities, including coupled lines, capacitors, and resistors, as well as a glossary of special functions.
Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Journal ArticleDOI
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters
Brian Floyd,Chih-Ming Hung +1 more
TL;DR: This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with anIntegrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.
Book
Interconnect analysis and synthesis
TL;DR: In this article, the authors present an overview and static topology optimization for On-chip Interconnects, including inductance and inductive coupling for on-chip interconnects.