Proceedings ArticleDOI
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure
K. Kiyoyama,K-W Lee,Takafumi Fukushima,Hideki Naganuma,Harufumi Kobayashi,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
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TLDR
The fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling array, and analog-to-digital converter (ADC) array is described, which proposes a blockparallel signal processing with three-dimensional structure.Abstract:
In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 ×100 μm2.read more
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Journal ArticleDOI
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture
Tomohiro Takahashi,Yuichi Kaji,Yasunori Tsukuda,Shinichiro Futami,Katsuhiko Hanzawa,Takahito Yamauchi,Ping Wah Wong,Frederick Brady,Phil Holden,Thomas Richard Ayers,Kyohei Mizuta,Susumu Ohki,Keiji Tatani,Hayato Wakabayashi,Yoshikazu Nitta +14 more
TL;DR: An intelligent sensor system with face detection derived from low-resolution images triggering high-resolution region-of-interest (ROI) output has been demonstrated with significantly reduced data bandwidth and low ADC power dissipation by utilizing the flexible area access function.
Journal ArticleDOI
A 3 Megapixel 100 Fps 2.8 $\mu$ m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers
TL;DR: The experimental results demonstrate the successful parallel output images of 3 megapixels with 16 × 8 modules at 100 fps, showing that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.
Journal ArticleDOI
A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors
TL;DR: A readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs, which reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield.
Proceedings ArticleDOI
Chip-based hetero-integration technology for high-performance 3D stacked image sensor
Yoshikazu Ohara,Kang-Wook Lee,K. Kiyoyama,S. Konno,Yutaka S. Sato,S. Watanabe,A. Yabata,H. Kobayashi,T. Kamada,Jichoel Bea,M. Murugesan,Hideki Hashimoto,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +14 more
TL;DR: Wang et al. as mentioned in this paper developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology.
Proceedings ArticleDOI
A 0.05mm 2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager
TL;DR: In this article, a two-step switching SAR ADC architecture was proposed to reduce the area and power consumption of the DAC network, and the total number of unit capacitors of the proposed approach is only 64C.
References
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