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A Digital Pixel Sensor Array With Programmable Dynamic Range A Digital Pixel Sensor Array With Programmable Dynamic Range
Alistair Kitchen
Edith Cowan University
Amine Bermak
Hong Kong University of Science and Technology
Abdesselam Bouzerdoum
University of Wollongong
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10.1109/TED.2005.859698 Kitchen, A. , Bermak, A., & Bouzerdoum, A. (2005). A Digital Pixel Sensor Array With
Programmable Dynamic Range. Transactions on Electron Devices, 52(12), 2591-2601. Available here
This Journal Article is posted at Research Online.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005 2591
A Digital Pixel Sensor Array With
Programmable Dynamic Range
Alistair Kitchen, Student Member, IEEE, Amine Bermak, Senior Member, IEEE, and
Abdesselam Bouzerdoum, Senior Member, IEEE
Abstract—This paper presents a digital pixel sensor (DPS) array
employing a time domain analogue-to-digital conversion (ADC)
technique featuring adaptive dynamic range and programmable
pixel response. The digital pixel comprises a photodiode, a voltage
comparator, and an 8-bit static memory. The conversion character-
istics of the ADC are determined by an array-based digital control
circuit, which linearizes the pixel response, and sets the conversion
range. The ADC response is adapted to different lighting condi-
tions by setting a single clock frequency. Dynamic range compres-
sion was also experimentally demonstrated. This clearly shows the
potential of the proposed technique in overcoming the limited dy-
namic range typically imposed by the number of bits in a DPS. A
64
64 pixel array prototype was manufactured in a 0.35- m,
five-metal, single poly, CMOS process. Measurement results indi-
cate a 100 dB dynamic range, a 41-s mean dark time and an average
current of 1.6
A per DPS.
Index Terms—CMOS imager, digital pixel sensor (DPS), self-re-
setting asynchronous pixel.
I. INTRODUCTION
C
HARGE-COUPLED DEVICE (CCD) imagers remain
in the forefront of commercial imaging technology, ex-
ploiting advanced manufacturing techniques to produce high
quality, high resolution images. However, recent developments
in CMOS image sensors have demonstrated the inherent advan-
tages of this technology, which are particularly attractive for
combined on-chip image acquisition and processing, featuring
low power and low manufacturing cost [1]. Technology scaling
has played a key role in introducing more intelligence and
further processing even at the pixel level. A digital pixel sensor
(DPS), which performs the analog-to-digital conversion (ADC)
at the pixel level, is an example of the new design concepts
made possible due to the scaling of CMOS devices to deep sub-
micrometer levels. Wandell
et al. have argued the importance
of multiple image capture, and the application of DPS arrays,
stressing the value of “local memory” within the imager [2].
In addition, very low-speed converters can be used and a high
Manuscript received May 3, 2005; revised September 6, 2005. This work was
supported in part by the Australian Research Council. The review of this paper
was arranged by Editor J. Hynecek.
A. Kitchen is with the School of Engineering and Mathematics, Edith Cowan
University, Joondalup 6027, Australia (e-mail: a.kitchen@ecu.edu.au).
A. Bermak is with the Department of Electrical and Electronic Engineering,
Hong Kong University of Science and Technology, Kowloon, Hong Kong
(e-mail: eebermak@ust.hk).
A. Bouzerdoum is with the School of Electrical, Computer and Telecommuni-
cations Engineering, University of Wollongong, Wollongong, NSW 2522, Aus-
tralia (e-mail: a.bouzerdoum@ieee.org).
Digital Object Identifier 10.1109/TED.2005.859698
level of parallelism is obtained using ADCs operating at only
tens of samples per second [3], [4]. An efficient exploitation
of the parallelism can reduce global power consumption and
speed-up data conversion, thus increasing the frame rate of the
imager [3], [5]. Additional benefits are also found in DPSs as
driving a large data bus using small on-pixel buffers is avoided
by the use of local on-pixel data-converters. While on-pixel
data conversion provides a number of advantages, there are still
many challenges and issues that remain to be solved. Indeed,
since the conversion in a DPS architecture takes place at the
pixel level, the dynamic range is limited by the number of
bits used for the conversion. Adaptation to different lighting
conditions and extended dynamic range required for natural
lighting scenes is very critical when designing DPS arrays.
One interesting way to improve the dynamic range of CMOS
imagers is to employ time-based conversion using self-reset-
ting architectures based on either pulse frequency modulation
(PFM) scheme [6]–[10] or pulse width modulation (PWM)
scheme [11]–[13]. The self-resetting scheme improves the
dynamic range by recycling the well such that higher photocur-
rents are detected. The output takes the form of a series of
spikes, resulting in the so-called “spiking pixel’ [7], which is of
particular interest when mimicking the processes of biological
vision [9]. This method presents several issues when dealing
with high resolution pixel array. One issue is related to the ac-
cess to the spiking pixel array which is provided by a complex
bus-arbitration system termed address event representation
(AER). Another problem encountered in the AER-based im-
agers is the temporal jitter due to the collision problem which
affects the SNR. In addition, the synchronous self-resetting
scheme suffers from higher dynamic power consumption as
the pixel is constantly allowed to fire whenever it reaches a
threshold voltage. Therefore, the power consumption of a large
array of free running pixels can be very significant. Further-
more, DPS is very inefficiently realized using the synchronous
self-resetting scheme as an area consuming digital counter is
required at the pixel level [6].
In this paper, a DPS array with a time-based ADC is pre-
sented. This proof-of-concept design is intended as an evalua-
tion testbed, to assess the suitability of the device for image cap-
ture, and develop low level image processing algorithms which
exploit the advantages of the DPS architecture. The pixel re-
lies on a single pulse (or pulsewidth modulation) as well as a
novel self-resetting approach using a pixel level SR latch. The
pulsewidth modulation (PWM) encoding reduces the dynamic
power consumption and preserves the advantage of wider dy-
namic range as each pixel sets its own integration time which
0018-9383/$20.00 © 2005 IEEE
2592 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005
Fig. 1. (a) Architecture of the DPS array based on the self-resetting asynchronous pixel. (b) Timing diagram.
is not dictated by a global timing circuit. The sensor also inte-
grates a pixel level memory, avoiding the need for AER type
of read-out and providing focal-plane image storage capability.
The conversion characteristics of the DPS are set using an array-
based control circuit which in fact provides the quantization
boundaries for the time domain conversion. One unique feature
of our sensor is the possibility to program these quantization
boundaries, effectively allowing the sensor response to adapt
to different lighting conditions. Linear and extended-range non
linear responses are experimentally demonstrated.
The remainder of this paper is organized as follows. Section II
describes the imager architecture, including a detailed descrip-
tion of the self-resetting pixel operation. The time domain ADC
is described in Section III, which includes simulation results of
the conversion process. Section IV details the very large-scale
integration (VLSI) implementation of the control circuit and the
pixel. Section V presents experimental results obtained from the
manufactured prototype. Section VI concludes the paper.
II. DPS W
ITH SELF-RESETTING ASYNCHRONOUS SCHEME
Fig. 1(a) and (b) shows the architecture of the self-resetting
asynchronous DPS and its timing diagram, respectively. The
architecture is similar in configuration to a single slope ADC,
and also to the DPS array of Kleinfelder et al. [5]. However,
our DPS array differs significantly from the other two architec-
tures in its mode of operation. The image acquisition starts by
sending a global start integration signal ST
, to the array and
to the control circuit. The control circuit generates timing data,
which is distributed in parallel to all the pixels of the array. Upon
receiving the start integration signal, each pixel operates asyn-
chronously, where the output voltage of the photodiode is com-
pared to a fixed reference voltage. When the two voltages be-
come equal, the comparator switches, and the data value, which
records the switching time, is stored in the pixel memory. The in-
tegration time is therefore not dictated by a global timing circuit
but is set by each pixel independently. Due to the asynchronous
nature of the pixel operation, it is necessary to distribute the
timing data as Gray code, to eliminate any errors that may have
been caused by the pixel comparator switching during data tran-
sition. A secondary benefit of distributing the data in Gray code
is reduced power consumption, as only one bit changes state
per clock cycle, and only one bus line has to be charged or dis-
charged. The photodetector operates in photon flux integration
mode, where the photocurrent is integrated over time in order to
produce a large change in the stored charge, and consequently,
the signal voltage. This mode of operation is commonly used
by most CMOS voltage mode photodetectors, and results in the
junction voltage decaying at a virtually constant rate, despite
the junction capacitance being voltage dependent [14]. The pho-
todiode sensor is reverse-biased by a fixed voltage source
,
which fully charges the photodiode junction capacitance
.
is then removed, and the junction capacitance is now discharged
by the leakage current of the diode, comprised of thermally and
optically generated carriers. In other sensor designs, this dis-
charge takes place for some fixed time period, after which
is
read and digitized, either at the array, column, or pixel level. The
alternative technique presented here allows
to discharge to a
fixed voltage reference,
. The time taken for this transition
is measured, and the result is stored in pixel memory. The op-
eration of the pixel, shown in Fig. 1(a), begins in the idle state,
with the node
held at by , which in turn is held ON by
the SR latch,
and . must be at least 2 below ,
where
is the n-type FET threshold voltage. If this were not
the case, variations in
, which is heavily process dependent,
would be reflected as fixed pattern noise (FPN) in the captured
KITCHEN et al.: DIGITAL PIXEL SENSOR ARRAY WITH PROGRAMMABLE DYNAMIC RANGE 2593
Fig. 2. Transistor level circuit diagram.
image. To begin the integration period, the signal ST is ap-
plied to the
input of the latch, switching the output states
and turning off
(via and ). With transistor now
open, the junction capacitance is discharged by the photocurrent
until
. At this point the comparator output switches
high, and the latch again changes state, rapidly recharging
,
and returning the circuit to the idle state. This ensures that
never reaches a level where the photodiode may be forward bi-
ased, hence avoiding “blooming” of the image. This also mini-
mizes the recharging current required for the subsequent image
capture, as
is never fully discharged. Fig. 2 shows the tran-
sistor level circuit diagram of each pixel comprised of a photo-
diode sensor, an analogue comparator, an SR latch, and an 8-bit
memory cell. The two-stage comparator includes a differential
first stage followed by a biased-inverter.
An analogue, rather than a clocked, comparator was chosen
to minimize the switching noise and to remove the need for mul-
tiphase clock distribution throughout the pixel array. Due to the
self resetting circuit, the maximum comparator output voltage is
typically 1.8 V, and must first be buffered to ensure reliable op-
eration of the memory. The transistors in the first inverter stage
are sized to lower the input threshold voltage to approximately
1.2 to 1.3 V, which provides an acceptable noise margin. The
comparator output splits into two paths: the first controlling the
self-resetting operation, and the second enabling the memory
for writing. Following the comparator is an SR latch, which con-
trols the self-resetting operation. Unlike in the PFM pixel, this
does not result in a free-running multivibrator, but instead the
pixel is held in a “ready” state at the end of each capture. The
capture cycle is defined by two distinct phases, namely the in-
tegration and the read-out phases. During the integration phase
the charges are collected during a pixels self-defined integration
time. During the read-out phase, the row and column decoders
are used to scan the contents of the in-pixel memories. The Q
and
outputs of the SR latch are buffered by and , and
are used to drive the reset transistor,
. The comparator output
is also used as the “write” signal for the 8-bit, in-pixel memory.
The memory is comprised of eight static latches, with a common
bus for writing and reading the timing data. The 8-bit, in-pixel
memory size was chosen as a compromise, between having suf-
ficient resolution to assess the performance of the imager, and
maintaining an acceptable fill factor for the pixel. Also, with
testing in mind, 8-bit resolution greatly simplifies interfacing,
storing and displaying of the image data. When reading data
from the array, each pixel is addressed by a ROW and COL se-
lect lines, derived from the address decoders located at the pe-
riphery of the array. This places the pixel data on the data bus,
which is then buffered to the chip output pins. The read opera-
tion is random, and nondestructive, allowing fast, repetitive ac-
cess to the image data. The memory can be cleared prior to the
next capture by placing null data on the bus, and pulsing
to , which will force a write operation. To reduce idle power
consumption, all voltage rails, except for
, can be disabled
between captures.
III. T
IME DOMAIN ADC
A. Blanking and Linearization Operation
The previous section described the operation of the asyn-
chronous pixel, and how the photocurrent is converted to a
variable width pulse. The time from the start signal
,to
the memory write signal will be referred to as the integration
time
. Two assumptions are made in deriving the ADC
algorithm 1) the photocurrent
, is large enough to disregard
other sources of leakage current and 2)
remains constant for
the integration period. The junction capacitance is dependent
upon voltage, and will be denoted as
. A small variation in
voltage
results in a charge accumulation of
(1)
Integrating (1) for a period
, corresponding to a voltage vari-
ation from
to , yields
(2)
where
. Therefore, the photocurrent ,is
inversely proportional to the integration period
(3)
where
.
2594 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005
The inverse relationship between the photocurrent and in-
tegration time must be compensated for by the ADC. If the
photocurrent is to be quantized uniformly, the integration time
must be quantized nonuniformly: small time steps for high pho-
tocurrents and large time steps for small photocurrents. This is
achieved by adjusting the count rate as the integration period
progresses. A down-counter is used, as the shortest integration
time corresponds to the highest illumination (or photocurrent) in
the scene. In order to determine the requirements of a time-based
ADC, some limits have to be placed on the range of the con-
version. Suppose the maximum photocurrent that is to be dig-
itized is
, which corresponds to the minimum integration
time
. The resolution of the conversion, , is determined
by the size of the in-pixel memory
(4)
where
is the number of bits of the in-pixel memory. The
smallest time step
is the difference between the integra-
tion times corresponding to
and :
Substituting for , using (4), and rearranging terms yields
(5)
Clearly, the dynamic range of the ADC (i.e.,
) can easily
be controlled by simply varying the minimum time step size,
: decreasing the minimum time step size increases the
dynamic range and vice versa. In other words, the time-based
ADC has a programmable dynamic range.
The timing counter must be driven at a frequency high enough
to resolve the smallest time step
. The smallest clock fre-
quency that achieves this is referred to as the primary clock fre-
quency,
1 . It follows from (5) that the primary
clock frequency is given by
2 2 (6)
It can be seen from (6) that the range of photocurrents, and hence
the range of illumination over which the ADC operates, can
be adjusted by varying the primary clock frequency
: in-
creasing the primary clock frequency increases the range of the
photocurrent. It should be noted that setting the maximum pho-
tocurrent by varying the primary clock frequency does not alter
the pixel operation, this can only be achieved by varying
or
, see (2).
Since minimum integration time, corresponding to
,
2 2 , the ADC conversion counter should
only start after
2 2 clock cycles. In other words, the con-
version process must be suppressed or “blanked’ for a period
equal to 2 2 clock pulses, after the integration
period begins. If the blanking period is not applied, only pho-
tocurrents higher than
can be digitized. Fig. 3 shows a
simulated ADC response with a primary clock frequency
set for an 55 pA. Here, the range of the photocurrent
is 100 pA, but obviously in a real scene the range may far
Fig. 3. Simulated ADC response using a fixed clock frequency and a blanking
period set for a maximum photocurrent
I
=
55 pA.
Fig. 4. ADC response using a variable frequency clock with a blanking period
set for a maximum photocurrent
I
=
55 pA.
exceed these limits. Pixels under high illumination will still
operate, and store the timing data, however if this occurs to
the right of
, the Gray counter output, used to encode the
digitized values, will remain static. It is only after the end of
the blanking period that the Gray code data changes, and the
different illumination levels are resolved (noting that as
and are inversely proportional, time progresses from right
to left in Fig. 3). While the pixels themselves have a very wide
operating range, the dynamic range of the captured image is
always limited by the size of the in-pixel memory (i.e., number
of bits). It can be seen from Fig. 3 that with a fixed clock the
count reaches zero with only half of the current range digitized,
resulting in the pixel memory being inefficiently utilized. To
overcome this, a variable frequency clock must be used.
It was shown previously (3) that the relationship between the
integration time and the photocurrent is nonlinear. Therefore,
if the in-pixel memory is to be used efficiently, the ADC must
compensate for this nonlinearity. This is accomplished by ad-
justing the frequency of the conversion clock as the conversion
period progresses, using the value of the conversion data (the
