Journal ArticleDOI
A High Power Density Series-Stacked Energy Buffer for Power Pulsation Decoupling in Single-Phase Converters
TLDR
In this paper, a high-efficiency, high-power-density buffer architecture is proposed for power pulsation decoupling in power conversion between dc and single-phase ac. In the proposed architecture, the main energy storage capacitor is connected in series with an active buffer converter across the dc bus.Abstract:
A high-efficiency, high-power-density buffer architecture is proposed for power pulsation decoupling in power conversion between dc and single-phase ac. We present an active decoupling solution that yields improved efficiency and reduced circuit complexity compared to existing solutions. In the proposed architecture, the main energy storage capacitor is connected in series with an active buffer converter across the dc bus. The series-stacked capacitor blocks the majority of the dc bus voltage to reduce the voltage stress on the buffer converter, such that fast, low-voltage transistors can be employed for the buffer converter. Moreover, the series capacitor provides the majority of the power pulsation decoupling through a wide voltage swing, and the buffer converter only needs to process a small fraction of the total power of the entire architecture, allowing a very small active circuit volume and very high system efficiency. The circuit operation and design constraints are analyzed in detail. In the proposed buffer architecture, the series stacking of a nearly lossless capacitor and a lossy converter presents a challenge of capacitor voltage balancing and power loss compensation. We propose a control scheme exploiting the small ripple in the bus voltage and dc input current to compensate for the power loss in the buffer converter while maintaining the voltage balance. Light-load techniques are also introduced to ensure that the buffer architecture meets strict ripple requirements while providing sufficient loss compensation. A 2-kW hardware prototype based on low-voltage GaN switches has been built to demonstrate the performance of the proposed solution. A power density of 25 W/cm $^3$ (410 W/in $^3$ ) by rectangular box volume and an efficiency above 98.9% across a wide load range has been experimentally verified.read more
Citations
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Journal ArticleDOI
A 2-kW Single-Phase Seven-Level Flying Capacitor Multilevel Inverter With an Active Energy Buffer
Yutian Lei,Christopher Barth,Shibin Qin,Wen-Chuen Liu,Intae Moon,Andrew Stillwell,Derek Chou,Thomas Foulkes,Zichao Ye,Zitao Liao,Robert C. N. Pilawa-Podgurski +10 more
TL;DR: In this article, the authors present a 2-kW, 60-Hz, 450-V -to-240-V power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge, which achieves a high power density of 216 W/in $3$ and a peak overall efficiency of 97.6%, while meeting the constraints including input current ripple, load transient, thermal, and FCC Class B EMC specifications.
Journal ArticleDOI
Review of Architectures Based on Partial Power Processing for DC-DC Applications
Jon Anzola,Iosu Aizpuru,Asier Arruti Romero,Argiñe Alacano Loiti,Ramon Lopez-Erauskin,J.S. Artal-Sevil,Carlos Bernal +6 more
TL;DR: This paper seeks to stablish a nomenclature that avoids confusion when indexing this type of architectures based on the partial power processing concept, whose main objective is to achieve a reduction of the power processed by the converter.
Journal ArticleDOI
A Two-Terminal Active Capacitor
Haoran Wang,Huai Wang +1 more
TL;DR: In this paper, the authors proposed a two-terminal active capacitor implemented by power semiconductor switches and passive elements, which can be specified by rated voltage, ripple current, equivalent series resistance, and operational frequency range.
Journal ArticleDOI
An Overview of Capacitive DC-Links-Topology Derivation and Scalability Analysis
TL;DR: A generic topology derivation method for single-phase power converters with active capacitive dc-link integrated has been proposed, which can derive all existing topologies, and identify a few new topologies.
Journal ArticleDOI
A High-Power-Density Power Factor Correction Front End Based on Seven-Level Flying Capacitor Multilevel Converter
TL;DR: A power factor correction (PFC) front end based on a seven-level flying capacitor multilevel (FCML) boost converter that features the use of low-voltage-rated transistors, reduced voltage stress, and high effective switching frequency on the filter inductor to significantly improve the power density of the PFC front end compared to conventional solutions.
References
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Journal ArticleDOI
Multilevel inverters: a survey of topologies, controls, and applications
TL;DR: The most important topologies like diode-clamped inverter (neutral-point clamped), capacitor-Clamped (flying capacitor), and cascaded multicell with separate DC sources are presented and the circuit topology options are presented.
Proceedings ArticleDOI
Multilevel converters-a new breed of power converters
Jih-Sheng Lai,Fang Zheng Peng +1 more
TL;DR: This paper presents three multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources.
Journal ArticleDOI
Reliability of Capacitors for DC-Link Applications in Power Electronic Converters—An Overview
Huai Wang,Frede Blaabjerg +1 more
TL;DR: This review serves to provide a clear picture of the state-of-the-art research in this area and to identify the corresponding challenges and future research directions for capacitors and their dc-link applications.
Journal ArticleDOI
Flyback-Type Single-Phase Utility Interactive Inverter With Power Pulsation Decoupling on the DC Input for an AC Photovoltaic Module System
TL;DR: In this paper, a flyback-type utility interactive inverter circuit topology was proposed for photovoltaic (PV) power generation systems when its lifetime under high atmospheric temperature is taken into account.
Journal ArticleDOI
Minimum Energy and Capacitance Requirements for Single-Phase Inverters and Rectifiers Using a Ripple Port
TL;DR: In this article, a ripple power port is proposed to manage energy storage and decouple capacitor ripple from power ripple, allowing the designer to make a choice of capacitor voltage independent of other system voltages.
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