Open AccessJournal Article
A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates
TLDR
The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic and the design has been compared with earlier proposed 4T and 6T Xor gates and a significant improvement in silicon area and power-delay product has been obtained.Abstract:
The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15 m and 0.35 m technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE. Keywords—XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.read more
Citations
More filters
Journal ArticleDOI
Area, Delay And Power Comparison Of Adder Topologies
TL;DR: The pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area is presented and ripple carry adder is presented.
Erratum: "Analysis and design strategy of UHF micro-power CMOS rectifiers for micro-sensor and RFID applications" (IEEE Transactions on Circuits and Systems I: Regular Papers)
TL;DR: A scheme for error compensation of arithmetic circuits in which a so-called padding is utilized to compensate at the output for the truncated bits of the input operands is proposed.
Journal ArticleDOI
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Hamed Naseri,Somayeh Timarchi +1 more
TL;DR: The proposed novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation.
Journal ArticleDOI
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Nabihah Ahmad,S. M. Rezaul Hasan +1 more
TL;DR: This paper presents a full custom CMOS design of S-Box/Inversion S- Box (Inv S- box) with low power GF (2^8) Galois Field inversions based on polynomial basis, using composite field arithmetic.
Journal ArticleDOI
On the Design of Approximate Restoring Dividers for Error-Tolerant Applications
TL;DR: The simulation results show that with extensive savings for power dissipation and circuit complexity, the proposed designs offer better error tolerant capabilities for quotient oriented applications (image processing) than remainder oriented application (modulo operations).
References
More filters
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Patent
Digital integrated circuits
TL;DR: Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
Journal ArticleDOI
Low-power logic styles: CMOS versus pass-transistor logic
R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Journal ArticleDOI
Performance analysis of low-power 1-bit CMOS full adder cells
TL;DR: A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.