Journal ArticleDOI
Performance analysis of low-power 1-bit CMOS full adder cells
TLDR
A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.Abstract:
A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.read more
Citations
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Journal ArticleDOI
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
TL;DR: The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.
Journal ArticleDOI
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Journal ArticleDOI
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
TL;DR: In this article, the authors investigated the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits.
Journal ArticleDOI
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
TL;DR: Two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP) outperform its counterparts exhibiting an average PDP advantage.
Journal ArticleDOI
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
TL;DR: In this paper, a hybrid 1-bit full adder design employing both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported and is found to offer significant improvement in terms of power and speed.
References
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Journal ArticleDOI
Low-power logic styles: CMOS versus pass-transistor logic
R. Zimmermann,Wolfgang Fichtner +1 more
TL;DR: This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.
Journal ArticleDOI
Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
TL;DR: In this paper, a simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits, based on the behavior of the inverter when loaded with different capacitances.
Journal ArticleDOI
New efficient designs for XOR and XNOR functions on the transistor level
TL;DR: In this article, two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level, one uses non-complementary signal inputs and the least number of transistors, while the other one improves the performance of the prior method but two more transistors are utilized.
Journal ArticleDOI
A new design of the CMOS full adder
Nan Zhuang,Haomin Wu +1 more
TL;DR: By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder, and they have desirable transfer characteristics.
Journal ArticleDOI
Circuit techniques for CMOS low-power high-performance multipliers
TL;DR: In this article, the authors presented circuit techniques for CMOS low-power high-performance multiplier design using 0.8-/spl mu/m CMOS (in BiCMOS) technology.