Journal ArticleDOI
A process-tolerant cache architecture for improved yield in nanoscale technologies
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TLDR
This technique dynamically detects and replaces faulty cells by dynamically resizing the cache and surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation.Abstract:Â
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. We analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under /spl sigma//sub Vt-inter/=/spl sigma//sub Vt-intra/=30 mV.read more
Citations
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Proceedings ArticleDOI
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
Onur Mutlu,Thomas Moscibroda +1 more
TL;DR: This paper proposes a new memory access scheduler, called the Stall-Time Fair Memory scheduler (STFM), that provides quality of service to different threads sharing the DRAM memory system and shows that STFM significantly reduces the unfairness in theDRAM system while also improving system throughput on a wide variety of workloads and systems.
Proceedings ArticleDOI
Process Variation Tolerant 3T1D-Based Cache Architectures
TL;DR: A range of cache refresh and placement schemes that are sensitive to retention time are proposed, and it is shown that most of the retention time variations can be masked by the microarchitecture when using these schemes.
Proceedings ArticleDOI
Exploring sub-20nm FinFET design with predictive technology models
TL;DR: Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research and PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.
Journal ArticleDOI
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era
Swaroop Ghosh,Kaushik Roy +1 more
TL;DR: In this article, the authors discuss the emerging paradigm of variation-tolerant adaptive design for both logic and memories, and present circuit and microarchitectural techniques to perform reliable computations in an unreliable environment.
Journal ArticleDOI
Reliability- and process-variation aware design of integrated circuits.
TL;DR: A broad review the literature for Reliability- and Process-variation aware VLSI design shows a re-emergence of the topic as a core area of active research and is likely to be a part of any reliability qualification protocol for future technology generations.
References
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Probability, random variables and stochastic processes
TL;DR: This chapter discusses the concept of a Random Variable, the meaning of Probability, and the axioms of probability in terms of Markov Chains and Queueing Theory.
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Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
The SimpleScalar tool set, version 2.0
Doug Burger,Todd Austin +1 more
TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.