Journal ArticleDOI
A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs
TLDR
In this article, a unified model for low resistivity metal-insulator-semiconductor (M-I-S) ohmic contact was developed for low conduction band offset.Abstract:
A comprehensive, physics-based unified model is developed for study of low resistivity metal-insulator-semiconductor (M-I-S) ohmic contact. Reduction in metal-induced gap state density and Fermi unpinning in semiconductor as a function of insulator thickness is coupled with electron transport including tunnel resistance through the metal-insulator-semiconductor (M-I-S) system to calculate specific contact resistivity at each insulator thickness for n-Si, n-Ge, and n-InGaAs. Low conduction band offset results in ∼1×10−9 Ω−cm2 contact resistivity with TiO2 insulator on n-Si, ∼7×10−9 Ω−cm2 can be achieved using TiO2 and ZnO on n-Ge, and ∼6×10−9 Ω−cm2 can be achieved with CdO insulator on n-InGaAs, which meet the sub-22nm CMOS requirements.read more
Citations
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Journal ArticleDOI
Band offsets, Schottky barrier heights, and their effects on electronic devices
TL;DR: In this paper, the authors review the band line-ups and band offsets between semiconductors, dielectrics, and metals, including the theory, experimental data, and the chemical trends.
Journal ArticleDOI
Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts
Ashish Agrawal,J. C. Lin,Michael Barth,Ryan M. White,Bo Zheng,Saurabh Chopra,Shashank Gupta,Ke Wang,Jerry Gelatos,Suzanne E. Mohney,Suman Datta +10 more
TL;DR: In this paper, the effect of reduction of ultrathin TiO2 by Ti and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied.
Journal ArticleDOI
Emerging Applications for High K Materials in VLSI Technology
TL;DR: The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed.
Journal ArticleDOI
Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer
Prashanth Paramahans Manik,R. K. Mishra,V. Pavan Kishore,Prasenjit Ray,Aneesh Nainani,Yi-Chiau Huang,Mathew Abraham,Udayan Ganguly,Saurabh Lodha +8 more
TL;DR: In this article, low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti have been reported on epitaxial n+-Ge (2.5×1019 cm−3) layers.
Journal ArticleDOI
Progress in Contact, Doping and Mobility Engineering of MoS2: An Atomically Thin 2D Semiconductor
Amritesh Rai,Hema C. P. Movva,Anupam Roy,Deepyanti Taneja,Sayema Chowdhury,Sanjay K. Banerjee +5 more
TL;DR: In this paper, a comprehensive overview of the various engineering solutions employed, thus far, to address the all-important issues of contact resistance (RC), controllable and area-selective doping, and charge carrier mobility enhancement in 2D molybdenum disulfide (MoS2)-based devices is presented.
References
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Book
Semiconductor Devices: Physics and Technology
TL;DR: In this paper, the transmission coefficient of a symmetric resonance tunneling diode has been derived for a Symmetric Resonant-Tunneling Diode, and it has been shown that it can be computed in terms of the Density of States in Semiconductor.
Journal ArticleDOI
Band offsets of wide-band-gap oxides and implications for future electronic devices
TL;DR: In this paper, the Schottky barrier heights and band offsets for high dielectric constant oxides on Pt and Si were calculated and good agreement with experiment is found for barrier heights.
Journal ArticleDOI
On the physics of metal-semiconductor interfaces
TL;DR: In this article, the authors describe the continuum of metal-induced gap states (MIGS) which are derived from the virtual gap states of the complex semiconductor band structure, and the physical mechanism primarily determining barrier height is provided by the decay of the metal's electron wavefunctions into the semiconductor in the energy range between the top of the valence band and the Fermi level.
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Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application
TL;DR: In this paper, an ultrathin interfacial silicon nitride layer was added to the metal/SiN/Ge Schottky diode to suppress strong Fermi level pinning, which resulted in effective control of Schotty barrier height.
Journal ArticleDOI
Fermi-level depinning for low-barrier Schottky source/drain transistors
TL;DR: By imposing an ultrathin insulator between low-work function metals and silicon, the Schottky barrier of the junction can be substantially reduced, decreasing junction resistance as discussed by the authors, and this approach, low-Schottky-barrier metal source/drain transistors with Mg and Yb as S/D metals are demonstrated.