Proceedings ArticleDOI
Analysis of snapback behavior on the ESD capability of sub-0.20 /spl mu/m NMOS
Ajith Amerasekera,V. Gupta,Karthik Vasanth,S. Ramaswamy +3 more
- pp 159-166
TLDR
In this paper, the self-biased lateral NPN operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined, and the effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mm, and 0.25 /spl m/m.Abstract:
The self-biased lateral NPN (LNPN) operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined. The effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mu/m, and 0.25 /spl mu/m. Specifically, the influence of gate oxides <30 /spl Aring/, and the effects of CoSi/sub 2/ and TiSi/sub 2/ are characterized with the purpose of defining process dependencies and design space. It is shown that as gate oxides get thinner, oxide breakdown may become a limiting factor depending on the LNPN properties. Furthermore, changes in LNPN current gain through process or design variations, and the substrate resistance, can be used to tune ESD performance. Hence, transistor design and process choices can be made to ensure that the LNPN is optimized for successful operation even for very thin gate oxides in sub-0.2 /spl mu/m technologies.read more
Citations
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Journal ArticleDOI
Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices
TL;DR: In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications, including mixed-signal performance, impact of process variations, and gate oxide reliability.
Proceedings ArticleDOI
Engineering the cascoded NMOS output buffer for maximum V/sub t1/
TL;DR: In this paper, the authors investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer, and demonstrate how bipolar turn-on characteristics change with buffer layout.
Proceedings ArticleDOI
Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design
TL;DR: In this paper, a detailed study of the nonuniform bipolar conduction phenomenon in single finger NMOS transistors and its implications for deep submicron ESD design is presented.
References
More filters
Journal ArticleDOI
On the Variation of Junction-Transistor Current-Amplification Factor with Emitter Current
TL;DR: In this paper, the authors take into account modification of the base region by the injected charge carriers, and find that the effect of surface recombination and increased current-amplification factor increases as the emitter current rises.
Journal ArticleDOI
The impact of technology scaling on ESD robustness and protection circuit design
A. Amerasekera,C. Duvvury +1 more
TL;DR: In this paper, the trend in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits.
Proceedings ArticleDOI
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
TL;DR: In this article, a circuit-level simulator for ESD and EOS is presented, which uses the three terminal currents obtained from a single high current I-V curve, and compared to experimental data for single devices as well as a practical output circuit.
Journal ArticleDOI
Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters
TL;DR: In this article, the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs were determined for use in the development of electrostatic discharge (ESD) protection circuits.