Proceedings ArticleDOI
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
A. Amerasekera,S. Ramaswamy,Mi-Chang Chang,Charvaka Duvvury +3 more
- pp 318-326
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TLDR
In this article, a circuit-level simulator for ESD and EOS is presented, which uses the three terminal currents obtained from a single high current I-V curve, and compared to experimental data for single devices as well as a practical output circuit.Abstract:
A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.read more
Citations
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Journal ArticleDOI
The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling
TL;DR: In this article, state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies is discussed, as well as emerging technologies.
Proceedings ArticleDOI
Substrate pump NMOS for ESD protection applications
TL;DR: In this article, a floating guardring is used to pump the local substrate of the protection NMOS to achieve uniform npn protection in a multi-finger NMOS for advanced CMOS technologies with silicide.
Journal ArticleDOI
Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes
TL;DR: This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes and shows how the PDN-MOS is effective even for small analog/mixed-signal designs.
Journal ArticleDOI
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations
TL;DR: In this article, a description of the behavior of the MOS device in the high current regime is presented together with the model equations governing that behaviour, and the equations have been implemented into a SPICE circuit simulator and the experimental and simulation results are given.
Journal ArticleDOI
Compact modeling of on-chip ESD protection devices using Verilog-A
TL;DR: A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented and a self-heating model is included for accurate simulation of the device ON-resistance under transient high- currents.
References
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Book
Device electronics for integrated circuits
TL;DR: In this article, the authors present a list of symbols for metal-oxide-silicon systems, including Mos Field-effect transistors, high-field effects, and high-frequency effects.
Journal ArticleDOI
High-gain lateral bipolar action in a MOSFET structure
TL;DR: In this paper, a hybrid-mode device based on a standard submicrometer CMOS technology is presented, in which the gate and well are internally connected to form the base of a lateral bipolar junction transistor (BJT).
Proceedings ArticleDOI
Dynamic gate coupling of NMOS for efficient output ESD protection
Charvaka Duvvury,Carlos H. Diaz +1 more
TL;DR: In this article, a dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported and the design issues for optimum output ESD protection are also discussed.
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