Proceedings ArticleDOI
Circuit aging prediction for low-power operation
Rui Zheng,Jyothi Velamala,Vijay Reddy,Varsha Balakrishnan,Evelyn Mintarno,Subhasish Mitra,Srikanth Krishnan,Yu Cao +7 more
- pp 427-430
TLDR
This work first examines critical model assumptions in the reaction-diffusion process that is responsible for the NBTI effect, and proposes a new aging model that effectively analyzes the degradation under various low-power operations and captures the essential role of the long recovery phase in circuit aging.Abstract:
Low-power circuit operations, such as dynamic voltage scaling and the sleep mode, pose a unique challenge to aging prediction. Traditional aging models assume constant voltage and averaged activity factor, ignoring the impact of the long sleep period, and thus, result in a significant overestimation of the degradation rate. To accurately predict the aging effect in low-power design, this work first examines critical model assumptions in the reaction-diffusion process that is responsible for the NBTI effect. By using the correct diffusion profile, it then proposes a new aging model that effectively analyzes the degradation under various low-power operations. The new model well predicts the aging behavior of scaled CMOS measurement data (45nm and 65nm) with different operation patterns, especially sleep mode operation and dynamic voltage scaling. Compared to previous aging models, the new result captures the essential role of the long recovery phase in circuit aging, reducing unnecessary guardbanding in reliability protection.read more
Citations
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Proceedings ArticleDOI
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Jorg Henkel,Lars Bauer,Nikil Dutt,Puneet Gupta,Sani R. Nassif,Muhammad Shafique,Mehdi B. Tahoori,Norbert Wehn +7 more
TL;DR: In this article, the authors introduce the most prominent reliability concerns from today's points of view and roughly recapitulate the progress in the community so far and suggest a way for coping with reliability challenges in upcoming technology nodes.
Journal ArticleDOI
Underdesigned and Opportunistic Computing in Presence of Hardware Variability
Puneet Gupta,Yuvraj Agarwal,Lara Dolecek,Nikil Dutt,Rajesh Gupta,Rakesh Kumar,Subhasish Mitra,Alexandru Nicolau,Tajana Rosing,Mani Srivastava,Steven Swanson,Dennis Sylvester +11 more
TL;DR: Specific sensing mechanisms that have been developed and their potential use in building underdesigned and opportunistic computing machines, including software stack that opportunistically adapts to a sensed or modeled hardware.
Proceedings ArticleDOI
A resilience roadmap
TL;DR: This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes, with the hope that it will invigorate research in this area.
Journal ArticleDOI
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
Evelyn Mintarno,Joëlle Skaf,Rui Zheng,Jyothi Velamala,Yu Cao,Stephen Boyd,Robert W. Dutton,Subhasish Mitra +7 more
TL;DR: The optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime.
Journal ArticleDOI
Overcoming Early-Life Failure and Aging for Robust Systems
TL;DR: This article presents novel system-level architecture and design innovations to cope with lifetime reliability challenges from three major sources: early-life failures, radiation-induced soft errors, and circuit aging.
References
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Journal ArticleDOI
Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
TL;DR: The negative bias temperature instability (NBTI) commonly observed in p-channel metaloxide-semiconductor field effect transistors when stressed with negative gate voltages at elevated temperatures is discussed in this article.
Proceedings ArticleDOI
Modeling and minimization of PMOS NBTI effect for robust nanometer design
TL;DR: A predictive model is developed for the degradation of NBTI in both static and dynamic operations and key insights are obtained for the development of robust design solutions.
Proceedings ArticleDOI
Predictive Modeling of the NBTI Effect for Reliable Design
TL;DR: This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation based on the reaction-diffusion (R-D) mechanism, which accurately captures the dependence of NBTI on the oxide thickness, the diffusing species and other key transistor and design parameters.
Book
Low Power Design Essentials
TL;DR: Low Power Design Essentials contains all the topics of importance to the low power designer including: optimization, architecture and algorithm level, memory, run time, standby logic, and standby memory.
Proceedings ArticleDOI
A critical examination of the mechanics of dynamic NBTI for PMOSFETs
TL;DR: In this paper, the authors examined the frequency-dependent shift in transistor parameters due to negative bias temperature instability (NBTI) using numerical and analytical solutions of the reaction diffusion model (R-D) and found that the magnitude of NBTI degradation depends on frequency through a complex interplay of reaction- and diffusion-limited trap generation processes.