Open AccessProceedings Article
Co-design methodology to provide high ESD protection levels in the advanced RF circuits
V. Vassilev,Steven Thijs,P. L. Segura,Paul Leroux,Piet Wambacq,Guido Groeseneken,M.I. Natarajan,Michiel Steyaert,Herman Maes +8 more
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TLDR
In this article, an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends, is described by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize.Abstract:
This paper describes an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends. The RF constraints on the ESD devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize. The method is applied to the design of 0.25 mum CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional high capacitive ggNMOS snapback devices.read more
Citations
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Book ChapterDOI
The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Journal ArticleDOI
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
TL;DR: An overview on E SD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented and the comparisons among these ESD protection designs are discussed.
Journal ArticleDOI
RF ESD protection strategies: Codesign vs. low-C protection
W. Soldner,Martin Streibl,U. Hodel,M. Tiebout,Harald Gossner,D. Schmitt-Landsiedel,Jung-Hoon Chun,C. Ito,Robert W. Dutton +8 more
TL;DR: The present work is focussed on the trade off between conventional RF E SD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design.
Proceedings ArticleDOI
Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies
TL;DR: S-parameter test structures show total capacitances per perimeter of ESD diodes increased, and two different BEOL wiring schemes are investigated for optimized metal coupling capacitance.
Proceedings ArticleDOI
CMOS Power Amplifier with ESD Protection Design Merged in Matching Network
TL;DR: A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18- mum CMOS process to alleviate loading that degrades RF performances.
References
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Journal Article
The design of CMOS radio-frequency integrated circuits, 2nd edition
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Book
The Design of CMOS Radio-Frequency Integrated Circuits
TL;DR: In this article, the authors present an expanded and thoroughly revised edition of Tom Lee's acclaimed guide to the design of gigahertz RF integrated circuits, which is packed with physical insights and design tips, and includes a historical overview of the field in context.
Proceedings ArticleDOI
Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process
TL;DR: In this article, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process and it appears clearly that a solution based on poly bounded diodes is the best choice.
Journal ArticleDOI
Investigation on different ESD protection strategies devoted to 3.3V RF applications (2GHz) in a 0.18μm CMOS process
TL;DR: In this article, the authors compared different ESD protection devices and showed that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme.
Journal ArticleDOI
High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection
Paul Leroux,Michel Steyaert +1 more
TL;DR: In this article, a new ESD protection methodology for high-frequency CMOS LNAs is introduced, where an on-chip inductor is employed to drain off the hazardous ESD charge while tuning out the harmful parasitic input capacitance.
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