Proceedings ArticleDOI
Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor
Norman Karl James,Phillip J. Restle,Joshua Friedrich,B. Huott,Bradley McCredie +4 more
- pp 298-604
TLDR
The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency than the split core power supply design.Abstract:
The POWER6trade is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disadvantages of each. On-chip noise measurements are compared to simulation. The noise measurements and simulation both show that the shorted core power grid design has less noise and a higher maximum frequency.read more
Citations
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Journal ArticleDOI
Three-dimensional silicon integration
John U. Knickerbocker,P.S. Andry,B. Dang,R. Horton,Mario J. Interrante,Chirag S. Patel,Robert J. Polastre,Katsuyuki Sakuma,R. Sirdeshmukh,Edmund J. Sprogis,Sri M. Sri-Jayantha,A. M. Stephens,Anna W. Topol,Cornelia K. Tsang,B. C. Webb,Steven L. Wright +15 more
TL;DR: 3D technology from IBM is highlighted, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and examples of 3D emerging industry product applications that could create marketable systems are provided.
Journal ArticleDOI
On the Interplay of Parallelization, Program Performance, and Energy Consumption
Sangyeun Cho,Rami Melhem +1 more
TL;DR: This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption and derives optimal frequencies allocated to the serial and parallel regions in an application to either minimize the total energy consumption or minimize the energy-delay product.
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Voltage emergency prediction: Using signatures to reduce operating margins
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Proceedings ArticleDOI
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Vijay Janapa Reddi,Svilen Kanev,Wonyoung Kim,Simone Campanoni,Michael D. Smith,Gu-Yeon Wei,David Brooks +6 more
TL;DR: It is shown that a voltage-noise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.
Proceedings ArticleDOI
On-chip timing uncertainty measurements on IBM microprocessors
R.L. Franch,Phillip J. Restle,Norman Karl James,William V. Huott,Joshua Friedrich,Robert Christopher Dixon,S. Weitzel,K. Van Goor,Gerard M. Salem +8 more
TL;DR: This paper describes the Skitter measurement experiences of several IBM microprocessors including PPC970MP, XBOX360TM, CELL Broadband EngineTM, and POWER6TM micro Processors running different workloads.
References
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Proceedings ArticleDOI
Design of the Power6 Microprocessor
Joshua Friedrich,Bradley McCredie,Norman Karl James,B. Huott,Brian W. Curran,Eric Fluhr,Gaurav Mittal,E. Chan,Y.H. Chan,Donald W. Plass,Sam Gat-Shang Chu,Hung Le,L. Clark,J. Ripley,Scott A. Taylor,Jack DiLullo,M. Lanzerotti +16 more
TL;DR: The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability.
Proceedings ArticleDOI
Timing uncertainty measurements on the Power5 microprocessor
Phillip J. Restle,R.L. Franch,Norman Karl James,William V. Huott,T.M. Skergan,S.C. Wilson,N. Schwartz,Joachim Gerhard Clabes +7 more
TL;DR: On-chip timing measurement (Skitter) circuits are included on the Power5 microprocessor by cross-coupling the 3 Skitter instances, so the combined effect of jitter, skew, and supply noise can be measured for all cycles of a pattern or an application.
Proceedings ArticleDOI
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor
TL;DR: The clock distribution network of the P0WER6 microprocessor is designed to run at frequencies exceeding 5GHz using only inverters and transmission lines and is capable of on-the-fly duty-cycle correction.
Proceedings ArticleDOI
A 64B CPU Pair: Dual- and Single-Processor Chips
Erwin B. Cohen,Norman J. Rohrer,Peter A. Sandon,M. Canada,Cedric Lichtenau,Mathew I. Ringler,Paul D. Kartschoke,R. Floyd,Jay G. Heaslip,M. Ross,T. Pflueger,Rolf Hilgendorf,P. McCormick,Gerard M. Salem,J. Connor,Stephen Frank Geissler,Dana J. Thygesen +16 more
TL;DR: Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology and the single-processor chip shares the dual's basic core and cache design.