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Journal ArticleDOI

Design and Analysis of CMOS Frequency Dividers With Wide Input Locking Ranges

TLDR
In this paper, two divide-by-2 (D2) and divideby-4 (D4) FDs were proposed to achieve the widest locking range reported to date by using a dual-mixing technique.
Abstract
A millimeter-wave (MMW) frequency synthesizer needs a low-power frequency divider (FD) with a wide input locking range to ensure reliability and lower power operation. In this paper, the design and analysis of low-power wide locking range MMW FDs are presented. Proposed are two divide-by-2 (D2) and divide-by-4 (D4) FDs that achieve the widest locking range reported to date by using a dual-mixing technique. Both FDs are fabricated in 90-nm CMOS and are demonstrated to achieve very wide input locking ranges without any tuning mechanism. At an input power of 0 dBm, the D2 FD has a locking range of 51-74 GHz, and that of the D4 FD is 82.5-89 GHz. The power consumption is only 3 mW for both the D2 FD and the D4 FD, from a 0.5 V supply. The proposed D2 and D4 FDs may facilitate incorporation into a product of a MMW phase-locked loop that is smaller, consumes less power, and is more reliable than the conventional approach.

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Citations
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Journal ArticleDOI

Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation

TL;DR: Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area.
Journal ArticleDOI

Analytical Approach to the Study of Injection-Locked Frequency Dividers

TL;DR: An analytical method for the nonlinear analysis of injection-locked frequency dividers (ILFDs) is presented based on the method of the slowly-varying amplitude and phase, which provides useful design insights.
Journal ArticleDOI

Design and Analysis of a 77.3% Locking-Range Divide-by-4 Frequency Divider

TL;DR: In this paper, a cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented, which consists of a divide-by-2 (D2) ILFD core and a source-injection current mode logic (SICML) divider.
Journal ArticleDOI

A General Theory of Injection Locking and Pulling in Electrical Oscillators—Part I: Time-Synchronous Modeling and Injection Waveform Design

TL;DR: A single first-order differential equation is shown to be capable of predicting a number of important properties, including the lock range, the relative phase of an injection-locked oscillator, and mode stability.
Journal ArticleDOI

Design and Analysis of a $W$ -band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique

TL;DR: In this paper, a W-band divide-by-three injection-locked frequency divider (ILFD) was designed and analyzed in 90 nm CMOS process, and the locking range is proportional to the device size of the injectors and amplitude of the injection signal.
References
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Journal ArticleDOI

Superharmonic injection-locked frequency dividers

TL;DR: In this article, a first-order differential equation is derived for the noise dynamics of injection-locked oscillators, and a single-ended ILFD is designed in a 0.5-/spl mu/m CMOS technology operating at 1.8 GHz with more than 190 MHz locking range while consuming 3 mW of power.
Journal ArticleDOI

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

TL;DR: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators, which features wide locking ranges, a very low input capacitance, and highest frequency capability.
Journal ArticleDOI

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

TL;DR: In this article, a regenerative divide topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances, achieving a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.
Proceedings ArticleDOI

A Highly Integrated 60GHz CMOS Front-End Receiver

TL;DR: A 60GHz CMOS front-end receiver is described, which comprises an LNA, a quadrature-balanced downconversion mixer, a VCO, and a frequency doubler.
Proceedings ArticleDOI

A 90nm CMOS 60GHz Radio

TL;DR: Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band.
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