Journal ArticleDOI
Design procedures for differential cascode voltage switch circuits
K.M. Chu,D.L. Pulfrey +1 more
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TLDR
Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented and are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions.Abstract:
Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.read more
Citations
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Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Journal ArticleDOI
A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
K.M. Chu,D.L. Pulfrey +1 more
TL;DR: A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques.
Journal ArticleDOI
Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid
L.S. Nielsen,Jens Sparsø +1 more
TL;DR: This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid, which re-implements an existing synchronous circuit which is used in a commercial product.
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Skew-Tolerant Circuit Design
TL;DR: Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers, and clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew.
Journal ArticleDOI
Performance of CMOS differential circuits
TL;DR: In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers and indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts.
References
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Proceedings ArticleDOI
Cascode voltage switch logic: A differential CMOS logic family
TL;DR: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described.
Book
Logic design and switching theory
TL;DR: Digital Logic Design Books & Lecture Notes Pdf Download Basic Logic Gates with Truth Tables Digital Logic CircuitsHigh Voltage Switchgear | Electrical4U
Journal ArticleDOI
Random logic design utilizing single-ended cascode voltage switch circuits in NMOS
TL;DR: A method is described for improving the functional efficiency of logic circuits through cascoding and a simultaneous reduction in power consumption can be achieved through a design example.
Journal ArticleDOI
A Method for Improving Cascode-Switch Macro Wirability
TL;DR: It is proved the problem is NP-complete, thus the existence of polynomial time algorithms is indeed unlikely, and an algorithm to find optimal solutions based on the principle of optimality is proposed.
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A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
K.M. Chu,D.L. Pulfrey +1 more