Development of the DEPFET sensor with signal compression: A large format X-ray imager with mega-frame readout capability for the European XFEL

TLDR: The DSSC instrument as mentioned in this paper is based on a silicon pixel sensor with a DEPFET as a central amplifier structure and has detection efficiency close to 100% for X-rays from 0.5 keV up to 10 keV.

Abstract: We present the development of the DSSC instrument: an ultra-high speed detector system for the new European XFEL in Hamburg. The DSSC will be able to record X-ray images with a maximum frame rate of 4.5 MHz. The system is based on a silicon pixel sensor with a DEPFET as a central amplifier structure and has detection efficiency close to 100% for X-rays from 0.5 keV up to 10 keV. The sensor will have a size of approximately 210 × 210 mm composed of 1024 × 1024 pixels with hexagonal shape. Two hundred fifty six mixed signal readout ASICs are bump-bonded to the detector. They are designed in 130 nm CMOS technology and provide full parallel readout. The signals coming from the sensor are processed by an analog filter, immediately digitized by 8-bit ADCs and locally stored in an SRAM, which is able to record at least 640 frames. In order to fit the dynamic range of about 104 photons of 1 keV per pixel into a reasonable output signal range, achieving at the same time single 1 keV photon resolution, a non-linear characteristic is required. The proposed DEPFET provides the needed dynamic range compression at the sensor level. The most exciting and challenging property is that the single 1 keV photon resolution and the high dynamic range are accomplished within the 220 ns frame rate of the system. The key properties and the main design concepts of the different building blocks of the system are discussed. Measurements with the analog front-end of the readout ASIC and a standard DEPFET have already shown a very low noise which makes it possible to achieve the targeted single photon resolution for 1 keV photons at 4.5 MHz and also for 0.5 keV photons at half of the speed. In the paper the new experimental results obtained coupling a single pixel to an 8 × 8 ASIC prototype are shown. This 8 × 8 ASIC comprises the complete readout chain from the analog front-end to the ADC and the memory. The characterization of a newly fabricated non-linear DEPFET is presented for the first time.