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Open AccessProceedings ArticleDOI

Digital sensitivity: predicting signal interaction using functional analysis

TLDR
It is found that it is possible to predict signal interaction by signal functionality alone, leading to a significant amount of robust switching isolation, independent of parasitics introduced by layout or semiconductor process.
Abstract
Maintaining signal integrity in digital systems is becoming increasingly difficult due to the rising number of analog effects seen in deep submicron design. One such effect, the signal crosstalk problem, is now a serious design concern. Signals which couple electrically may not affect system behavior because of timing or function in the digital domain. If we can isolate observable coupling effects then we can constrain layout synthesis to eliminate them. In this paper, we find that it is possible to predict signal interaction by signal functionality alone, leading to a significant amount of robust switching isolation, independent of parasitics introduced by layout or semiconductor process. We introduce techniques to predict signal interaction using functional sensitivity analysis. In general sequential networks we find that significant switching isolation can be extracted with efficient sensitivity analysis algorithms, thus giving promise to the goal of synthesizing layout free from crosstalk effects.

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Citations
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Journal ArticleDOI

Harmony: static noise analysis of deep submicron digital integrated circuits

TL;DR: A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulation-based transistor-level analysis.
Patent

Method for verification of crosstalk noise in a CMOS design

TL;DR: In this article, a methodology is provided that is a practical approach to full-chip crosstalk noise verification, using either timing information or functional information, and a grouping based method is described for identification of potential victims and associated aggressors.
Proceedings ArticleDOI

Timing and crosstalk driven area routing

TL;DR: A timing and crosstalk driven router for the chip assembly task that is applied between global and detailed routing, and a graph-based optimizer that preroutes wires on the global routing grids incrementally in two stages - net order assignment and space relaxation.
Proceedings ArticleDOI

A novel VLSI layout fabric for deep sub-micron applications

TL;DR: A new VLSI layout methodology which addresses the main problems faced in deep sub-micron (DSM) integrated circuit design, and shows how the uniform parasitics of the fabric give rise to a reliable and predictable design.
Book

Cross-talk noise immune VLSI design using regular layout fabrics

TL;DR: This work validated deep sub-Micron effects in a Network of PLAS using VLSI Layout Fabrics, a novel approach to fabric cell based design that reduces the uncertainty in the design of fabrics.
References
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Book

Digital Systems Testing and Testable Design

TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Proceedings ArticleDOI

Implicit state enumeration of finite state machines using BDD's

TL;DR: In this article, the authors propose a method based on transition relations that only requires the ability to compute the binary decision diagram for f/sub i/ and outperforms Coudert's (1990) algorithm for most examples.
Book

A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits

TL;DR: A top-down, constraint-driven design methodology for analog integrated circuits and some of the tools that support this methodology are described, including behavioral simulation tools, tools for physical assembly, and module generators.
Journal ArticleDOI

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

TL;DR: In this paper, a logic level characterization and fault model for crosstalk faults is presented, and a fault list of such faults can be generated from the layout data, and given an automatic test pattern generation procedure for them.