Imbalance Current Analysis and Its Suppression Methodology for Parallel SiC MOSFETs with Aid of a Differential Mode Choke

TLDR: It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.

Abstract: Parallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn- on and - off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn- off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.

Figures

Fig. 8. Imbalance current affected by unequal Tj at IL = 30 A. (a) Δid versus ΔTj and vgs, (b) Δid versus ΔTj and f, (c) mapped Δid versus f at Vth = 2 V, and (d) mapped Δid versus f at Vth = 4 V.

Fig. 9. Magnetic flux densities of DMC induced by (a) balance current id1 = id2 and (b) imbalance current id1 > id2.

Fig. 21. Extension of proposed DMC-based suppression method to multiple parallel SiC MOSFETs. (a) Geometry 1 and (b) geometry 2.

Fig. 22. Comparison of imbalance current suppression methods with respect to (a) electric indices, (b) safety indices, and (c) economic indices. A: DBC layout, B: series resistor, C: active gate driver, D: passive balancing, E: DMC.

Fig. 11. Test rig for parallel SiC MOSFETs. (a) Schematic of test rig, (b) structure of DMC, and (c) equivalent circuit of test rig.

Fig. 12. Transient imbalance current ratio limited by Lm. (a) γ versus Lm and f, (b) mapped γ and Lm at tr = 25 ns, and (c) mapped γ and Lm at tr = 10 ns.