Journal ArticleDOI
Impact of power-supply noise on timing in high-frequency microprocessors
M. Saint-Laurent,Madhavan Swaminathan +1 more
- Vol. 27, Iss: 1, pp 135-144
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In this article, the impact of power-supply noise on the performance of high-frequency microprocessors is analyzed. But the authors focus on the average supply voltage during switching.Abstract:
This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduces clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation.read more
Citations
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Journal ArticleDOI
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
Massimo Alioto,Gaetano Palumbo +1 more
TL;DR: It is shown that the delay sensitivity to supply variations will increase in the next technology nodes, thus, it is expected that controlling the supply variation will be an increasingly important issue in the design of the next generation VLSI circuits.
Proceedings ArticleDOI
Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform
TL;DR: In this work, power delivery network for 3D SIP integrated on silicon interposer, which includes integrated decoupling capacitor, gives good power delivery performance.
Journal ArticleDOI
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations
TL;DR: The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies.
Journal ArticleDOI
Architecture implications of pads as a scarce resource
TL;DR: In this paper, the authors develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation techniques, and the consequent implications of electromigration-induced PDN pad failure.
Architecture Implications of Pads as a Scarce Resource: Extended Results
TL;DR: This paper develops a pre-RTL PDN model, VoltSpot, and demonstrates that, despite their integral role in the PDN, power/ground pads can be aggressively reduced to their electromigration limit with minimal performance impact from extra voltage noise - provided the system implements a suitable noise-mitigation strategy.
References
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Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
The future of wires
R. Ho,Ken Mai,Mark Horowitz +2 more
TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.
Journal ArticleDOI
A clock distribution network for microprocessors
Phillip J. Restle,Timothy G. McNamara,David A. Webber,Peter J. Camporese,K.F. Eng,Keith A. Jenkins,D.H. Allen,M.J. Rohn,M.P. Quaranta,David William Boerstler,Charles J. Alpert,C.A. Carter,R.N. Bailey,J.G. Petrovick,Byron L. Krauter,Bradley McCredie +15 more
TL;DR: A global clock distribution strategy implemented on several microprocessor chips is described, which consists of buffered, tunable tree networks, with the final trees all driving a common grid.
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