Journal ArticleDOI
Input waveform slope effects in CMOS delays
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TLDR
Corrections of previously defined closed-form equations are proposed, allowing accurate evaluation of delays in a large range of configurations, and remain sufficiently manageable to be used in an automatic data-path sizing tool.Abstract:
Slow input ramp effects in delay evaluation on CMOS structures are considered. Corrections of previously defined closed-form equations are proposed, allowing accurate evaluation of delays in a large range of configurations. The expressions obtained remain sufficiently manageable to be used in an automatic data-path sizing tool. >read more
Citations
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Journal ArticleDOI
Gate sizing for constrained delay/power/area optimization
TL;DR: In this article, the gate sizing algorithm (GS) is proposed to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obtain the fastest circuit within a given power budget.
Journal ArticleDOI
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay
TL;DR: In this article, an improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered.
Journal ArticleDOI
A comprehensive delay macro modeling for submicrometer CMOS logics
J.M. Daga,D. Auvergne +1 more
TL;DR: A comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators is proposed, considering input slope, input-to-output capacitance coupling, and short-circuit current effects for CMOS inverters.
Journal ArticleDOI
A comprehensive delay model for CMOS inverters
TL;DR: It is found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times, and the delay equations also explain negative delays that arise in case of slow input rise-times.
Journal ArticleDOI
Propagation delay and short-circuit power dissipation modeling of the CMOS inverter
TL;DR: In this article, an accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter is presented. But the model does not take into account the influences of the shortcircuit current during switching, and the gate-to-drain coupling capacitance.
References
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Journal ArticleDOI
Explicit formulation of delays in CMOS data paths
TL;DR: In this paper, an explicit formulation of the transient response of general combinational CMOS structures, including load conditions and driving waveforms, is presented, based on data-path decomposition in unidirectional elementary cells, which allows an analytic formulation of real temporal behaviour of inverters, transmission gate arrays, and general CMOS gates.
Proceedings ArticleDOI
Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits
TL;DR: The XTRAS (Xerox TRAnsistor Sizing Program) as mentioned in this paper is a program that automatically determines transistor sizes as well as calculates path delays in CMOS digital circuits.
Journal ArticleDOI
A Fast-Timing Simulator for Digital MOS Circuits
D. Tsao,Chin-Fu Chen +1 more
TL;DR: An efficient and accurate algorithm has been developed for predicting the timing waveforms of general MOS transistor circuits and has been implemented as a new simulation mode in the MOTIS3 multilevel mixed-mode simulator.
Journal ArticleDOI
Explicit formulation of delays in CMOS VLSI
TL;DR: An explicit formulation for the transient response of CMOS inverters is given, including load conditions and driving waveforms, which shows clear evidence of the influence of structural and parasitic parameters on propagation times, allowing fast optimisation of the data path.
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