Proceedings ArticleDOI
Low power dual edge triggered flip flop using multi threshold CMOS
Ashish Kumar,Yogendera Kumar,Deepak Berwal +2 more
- Vol. 2016, pp 1358-1361
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TLDR
Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.Abstract:
In this work, a low power dual edge triggered flip flop design using multi threshold CMOS is proposed. Proposed Flip-Flop (FF) has three new feature points. First point, the pulse generation control logic is designed with EXOR gate and inverter chain which reduces the complexity and extra switching in pulse generator circuit. Second point, signal feed through technique with some modification is devised to speed up the charging and discharging along the critical path only when needed. Third point, multi-threshold CMOS technique is also applied to get low power dissipation. As a result, no. of transistors in pulse-generation circuit has been reduced for power and area saving. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.read more
Citations
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Journal ArticleDOI
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
TL;DR: A novel architecture for the pulse-triggered D-FF in the CMOS 90-nm technology utilizes a transmission gate to control the input data and the leakage power and has improvement in terms of power consumption, D-to-Q delay, and Power Delay Performance (PDP) in comparison with other D-Flip-Flop architectures.
Journal ArticleDOI
Low power aware pulse triggered flip flops using modified clock gating approaches
TL;DR: The study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs, and a reduction in power consumption is achieved.
Proceedings ArticleDOI
Design of a Sequential Circuit Based on Multi-Threshold FinFET Technique
TL;DR: This work integrates the multi-threshold technique with the FinFET technology to implement a master-slave data flip flop and compared the results obtained with the single threshold master slave data flipFlop and it has been observed that the static and average power consumption by the Flip flop has been reduced.
References
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Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
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1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Book
Design of High-Performance Microprocessor Circuits
TL;DR: The design of next generation microprocessors in deep submicron CMOS technologies is covered, and a broad range of circuit styles and VLSI design techniques are covered, an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers.
Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.