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Measurement of inherent noise in EDA tools

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TLDR
This work seeks to identify sources of noise in EDA tools, and analyze the effects of these noise sources on design quality, and proposes new behavior criteria for tools with respect to the existence and management of noise.
Abstract
With advancing semiconductor technology and exponentially growing design complexities, predictability of design tools becomes an important part of a stable top-down design process. Prediction of individual tool solution quality enables designers to use tools to achieve best solutions within prescribed resources, thus reducing design cycle time. However, as EDA tools become more complex, they become less predictable. One factor in the loss of predictability is inherent noise in both algorithms and how the algorithms are invoked. In this work, we seek to identify sources of noise in EDA tools, and analyze the effects of these noise sources on design quality. Our specific contributions are: (i) we propose new behavior criteria for tools with respect to the existence and management of noise; (ii) we compile and categorize possible perturbations in the tool use model or tool architecture that can be sources of noise; and (iii) we assess the behavior of industry place and route tools with respect to these criteria and noise sources. While the behavior criteria give some guidelines for and characterize the stability of tools, we are not recommending that tools be immune from input perturbations. Rather, the categorization of noise allows us to better understand how tools will or should behave; this may eventually enable improved tool predictors that consider inherent tool noise.

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Methodology from chaos in IC implementation

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Quantified Impacts of Guardband Reduction on Design Process Outcomes

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References
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Journal ArticleDOI

Asymptotic global behavior for stochastic approximation and diffusions with slowly decreasing noise effects: Global minimization via Monte Carlo

TL;DR: In this article, the authors studied the asymptotic behavior of the systems where the objective function values can only be sampled via Monte Carlo, where the discrete algorithm is a combination of stochastic approximation and simulated annealing.
Journal ArticleDOI

Random search in the presence of noise, with application to machine learning

TL;DR: A search for the global minimum of a function is proposed; the search is on the basis of sequential noisy measurements and the search plan is shown to be convergent in probability to a set of minimizers.
Journal ArticleDOI

Design and implementation of move-based heuristics for VLSI hypergraph partitioning

TL;DR: A detailed software architecture is presented that allows flexible, efficient and accurate assessment of the practical implications of new move-based algorithms and partitioning formulations and discusses the current level of sophistication in implementation know-how and experimental evaluation.
Proceedings ArticleDOI

Analysis of Placement Procedures for VLSI Standard Cell Layout

TL;DR: It is found that the Min Cut partitioning with simplified Terminal Propagation is the most efficient placement procedure studied and mean results of many placements should be used when comparing algorithms.
Proceedings ArticleDOI

Pre-layout estimation of individual wire lengths

TL;DR: There is inherent variability in wire lengths obtained using commer- cially available place and route tools - wire length estimation error cannot be any smaller than a lower limit due to this variability, and the proposed model works well within these variability limitations.
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