Journal ArticleDOI
Nanowire-based programmable architectures
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TLDR
This work develops nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices.Abstract:
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.read more
Citations
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Proceedings ArticleDOI
Diversity mapping scheme for defect and fault tolerance in nanoelectronic crossbar
TL;DR: A concept of diversity mapping and three corresponding algorithms for defect-tolerance logic mapping in nanoelectronic crossbar and can achieve several or ten times higher logic mapping success rates compared to the best recently published technique over a set of samples with various problem sizes.
Book ChapterDOI
Development and Analysis of Defect Tolerant Bipartite Mapping Techniques for Programmable cross-points in Nanofabric Architecture
TL;DR: In this article, a non-probabilistic approach for defect tolerance was proposed and evaluated in terms of its coverage for different sizes of fabric and different defect rates, and the defect rates can be as high as 13% or more.
Developing Fault Models for Nanowire Logic Circuits
TL;DR: In this paper, a fault model for nanowire logic circuits is proposed, which attends to how fault mechanisms manifest at device and logic, and how to deduce related fault models.
A Novel Reconfiguration Scheme in Quantum-Dot Cellular Automata for Energy Efficient Nanocomputing
TL;DR: A NOVEL RECONFIGURATION SCHEME in QUANTUM-DOT CELLULAR AUTOMATA for ENERGY EFFICIENT NANOCOMPUTING and its applications in novel energy efficiency and zero-emission vehicle development.
Proceedings ArticleDOI
Defect-tolerant logic hardening for crossbar-based nanosystems
Yehua Su,Wenjing Rao +1 more
TL;DR: This paper proposes an analytical framework to evaluate and fine-tune the amount and location of redundancy to be added for a given logic function and devise a method to optimally harden the logic function so as to maximize the defect tolerance capability.
References
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A laser ablation method for the synthesis of crystalline semiconductor nanowires
TL;DR: Studies carried out with different conditions and catalyst materials confirmed the central details of the growth mechanism and suggest that well-established phase diagrams can be used to predict rationally catalyst materials and growth conditions for the preparation of nanowires.
Journal ArticleDOI
Growth of nanowire superlattice structures for nanoscale photonics and electronics.
Mark S. Gudiksen,Lincoln J. Lauhon,Jianfang Wang,David C. Smith,Charles M. Lieber,Charles M. Lieber +5 more
TL;DR: Single-nanowire photoluminescent, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.
Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Journal ArticleDOI
Directed Assembly of One-Dimensional Nanostructures into Functional Networks
TL;DR: It is shown that nanowires can be assembled into parallel arrays with control of the average separation and, by combining fluidic alignment with surface-patterning techniques, that it is also possible to control periodicity.