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Journal ArticleDOI

Nanowire-based programmable architectures

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TLDR
This work develops nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices.
Abstract
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

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Book

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

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TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Book

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Self-organized computation with unreliable, memristive nanodevices

TL;DR: This work proposes to mitigate device shortcomings and exploit their dynamical character by building self-organizing, self-healing networks that implement massively parallel computations, useful for complex pattern recognition problems.
References
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Journal ArticleDOI

Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

TL;DR: In this paper, the memory characteristics as a function of channel widths for different channel lengths are presented, and the results show that the Si-NCs memory is highly scalable in terms of the channel size.
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