Journal ArticleDOI
Nanowire-based programmable architectures
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TLDR
This work develops nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices.Abstract:
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.read more
Citations
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Journal ArticleDOI
A Reconfigurable PLA Architecture for Nanomagnet Logic
TL;DR: This study presents an NML programmable logic array (PLA) based on a previously proposed reprogrammable quantum-dot cellular automata PLA design, and uses results from this study to shape a concluding discussion about which architectures appear to be most suitable for NML.
Proceedings ArticleDOI
Comparison of analog and digital nanosystems: Issues for the nano-architect
TL;DR: It is seen that while an analog nanoscale implementation of the CNN may be difficult with self-assembly based approaches given the requirements for customization of devices and arbitrary routing, a digital equivalent may be realizable in the near term.
Journal ArticleDOI
Enabling design and simulation of massive parallel nanoarchitectures
Stefano Frache,Diego Chiabrando,Mariagrazia Graziano,Marco Vacca,Luca Boarino,Maurizio Zamboni +5 more
TL;DR: The tool presented enables the designer to start from a standard High-level Description Languages (HDLs), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections.
Proceedings ArticleDOI
TAMTAMS: An open tool to understand nanoelectronics
Marco Vacca,Giovanna Turvani,Fabrizio Riente,Mariagrazia Graziano,Danilo Demarchi,Gianluca Piccinini +5 more
TL;DR: A tool “made by students for other students” which analyzes and compares different technologies from nanoscale CMOS transistors to emerging technologies, based for example on Carbon Nanotubes and Silicon Nanowires, and allows the evaluation of different circuit parameters.
Journal ArticleDOI
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
TL;DR: This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures and introduces a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time.
References
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Journal ArticleDOI
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TL;DR: Single-nanowire photoluminescent, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.
Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Journal ArticleDOI
Directed Assembly of One-Dimensional Nanostructures into Functional Networks
TL;DR: It is shown that nanowires can be assembled into parallel arrays with control of the average separation and, by combining fluidic alignment with surface-patterning techniques, that it is also possible to control periodicity.