Journal ArticleDOI
Nanowire-based programmable architectures
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TLDR
This work develops nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices.Abstract:
Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.read more
Citations
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DissertationDOI
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High-Performance, Fault-Tolerant Architecture for Reliable Hybrid Nanolectronic Memories
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References
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A laser ablation method for the synthesis of crystalline semiconductor nanowires
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Journal ArticleDOI
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Mark S. Gudiksen,Lincoln J. Lauhon,Jianfang Wang,David C. Smith,Charles M. Lieber,Charles M. Lieber +5 more
TL;DR: Single-nanowire photoluminescent, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.
Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Journal ArticleDOI
Directed Assembly of One-Dimensional Nanostructures into Functional Networks
TL;DR: It is shown that nanowires can be assembled into parallel arrays with control of the average separation and, by combining fluidic alignment with surface-patterning techniques, that it is also possible to control periodicity.