Proceedings ArticleDOI
NVM duet: unified working memory and persistent store architecture
Ren-Shuo Liu,De-Yu Shen,Chia-Lin Yang,Shun-Chih Yu,Cheng-Yuan Michael Wang +4 more
- Vol. 49, Iss: 4, pp 455-470
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TLDR
A novel unified working memory and persistent store architecture, NVM Duet, which provides the required consistency and durability guarantees for persistent store while relaxing these constraints if accesses to NVM are for working memory is proposed.Abstract:
Emerging non-volatile memory (NVM) technologies have gained a lot of attention recently. The byte-addressability and high density of NVM enable computer architects to build large-scale main memory systems. NVM has also been shown to be a promising alternative to conventional persistent store. With NVM, programmers can persistently retain in-memory data structures without writing them to disk. Therefore, one can envision that in the future, NVM will play the role of both working memory and persistent store at the same time. Persistent store demands consistency and durability guarantees, thereby imposing new design constraints on the memory system. Consistency is achieved at the expense of serializing multiple write operations. Durability requires memory cells to guarantee non-volatility and thus reduces the write speed. Therefore, a unified architecture oblivious to these two use cases would lead to suboptimal design. In this paper, we propose a novel unified working memory and persistent store architecture, NVM Duet, which provides the required consistency and durability guarantees for persistent store while relaxing these constraints if accesses to NVM are for working memory. A cross-layer design approach is adopted to achieve the design goal. Overall, simulation results demonstrate that NVM Duet achieves up to 1.68x (1.32x on average) speedup compared with the baseline design.read more
Citations
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Proceedings ArticleDOI
NV-Tree: reducing consistency cost for NVM-based single level systems
TL;DR: NV-Tree, a consistent and cache-optimized B+Tree variant with reduced CPU cacheline flush, and NV-Store, a key-value store based on NV- tree, are implemented and evaluated on an NVDIMM server.
Journal ArticleDOI
A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems
Sparsh Mittal,Jeffrey S. Vetter +1 more
TL;DR: A survey of software techniques that have been proposed to exploit the advantages and mitigate the disadvantages of NVMs when used for designing memory systems, and, in particular, secondary storage and main memory.
Proceedings ArticleDOI
An Analysis of Persistent Memory Use with WHISPER
TL;DR: The Hands-off Persistence System (HOPS) is proposed to track updates to PM in hardware to provide high-level ISA primitives for applications to express durability and ordering constraints separately and enforces them automatically, while achieving 24.3% better performance over current approaches to persistence.
Proceedings ArticleDOI
ThyNVM: enabling software-transparent crash consistency in persistent memory systems
TL;DR: A hardware-assisted DRAM+NVM hybrid persistent memory design, Transparent Hybrid NVM (ThyNVM), which supports software-transparent crash consistency of memory data in a hybrid memory system and efficiently enforce crash consistency through a new dual-scheme checkpointing mechanism.
Proceedings ArticleDOI
Delegated persist ordering
Aasheesh Kolli,Jeffrey Rosen,Stephan Diestelhorst,Ali G. Saidi,Steven Pelley,Sihang Liu,Peter M. Chen,Thomas F. Wenisch +7 more
TL;DR: Delegated ordering is proposed, wherein ordering requirements are communicated explicitly to the PM controller, fully decoupling PM write ordering from volatile execution and cache management, and it is demonstrated that delegated ordering can bring performance within 1.93x of volatile execution, improving over SO by 3.73x.
References
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Proceedings Article
QEMU, a fast and portable dynamic translator
TL;DR: QEMU supports full system emulation in which a complete and unmodified operating system is run in a virtual machine and Linux user mode emulation where a Linux process compiled for one target CPU can be run on another CPU.
Proceedings ArticleDOI
Architecting phase change memory as a scalable dram alternative
TL;DR: This work proposes, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM.
Proceedings ArticleDOI
Scalable high performance main memory system using phase-change memory technology
TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.
Journal ArticleDOI
Phase-change random access memory: a scalable technology
Simone Raoux,Geoffrey W. Burr,Matthew J. Breitwisch,Charles T. Rettner,Y.-C. Chen,Robert M. Shelby,Martin Salinga,Daniel Krebs,Shih-Hung Chen,H.L. Lung,Chung H. Lam +10 more
TL;DR: This work discusses the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms, and discusses experiments that directly address the scaling properties of the phase-change materials themselves.
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A durable and energy efficient main memory using phase change memory technology
TL;DR: The results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency and the design choices of implementing PCM to achieve the best tradeoff between energy and performance.