Journal ArticleDOI
Optimization of the latching pulse for dynamic flip-flop sensors
W.T. Lynch,H.J. Boll +1 more
TLDR
In this article, the authors analyzed dynamic IGFET flip-flop sensors and showed that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope.Abstract:
Analysis of dynamic IGFET flip-flop charge sensors shows that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope. Latchup time is approximately inversely proportional to the initial voltage imbalance. Capacitive coupling between the two sides of the flip-flop generates a voltage excursion of the off-side even when there is no off-side conduction. With a 10-V latching ramp, the off-side is no off-side conduction. With a 10-V latching ramp, the off-side voltage excursion is typically about 2 V, and full latchup is attained in about 75 ns for an initial imbalance of 0.5 V. If a small off-side conduction is allowed, then latchup time can be reduced by a factor of two or more. The penalty is a few tenths of a volt added excursion of the off-side voltage. Computer circuit simulations were used to verify the analytic derivations.read more
Citations
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Journal ArticleDOI
Yield and speed optimization of a latch-type voltage sense amplifier
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Journal ArticleDOI
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC
Howard Leo Kalter,C.H. Stapper,John E. Barth,J. Dilorenzo,Charles Edward Drake,John A. Fifield,Gordon Arthur Kelley,Scott C. Lewis,W.B. van der Hoeven,James Andrew Yankosky +9 more
TL;DR: A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described.
Patent
Semiconductor memory device.
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
Journal ArticleDOI
A fault-tolerant 64K dynamic random-access memory
Ronald Paul Cenker,Donald Gordon Clemons,William Richard Huber,J.B. Petrizzi,Frank John Procyk,G.M. Trout +5 more
TL;DR: A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized, which holds power and peak current values below those of 16K parts.
Journal ArticleDOI
High sensitivity charge-transfer sense amplifier
TL;DR: In this paper, a balanced charge-transfer sense amplifier for one-device cell memory arrays is presented, where charge transfer techniques are used to preamplify the sense signal and isolate the large bit/sense (B/S) line capacitance from the nodes of a dynamic latch.
References
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Journal ArticleDOI
Design of a high-performance 1024-B switched capacitor p-channel IGFET memory chip
H.J. Boll,W.T. Lynch +1 more
TL;DR: In this article, the IGA switched-capacitor memory cells are incorporated into a fully decoded dynamic, 1024-word by 1-b p-channel random access memory.