Proceedings ArticleDOI
Performance-driven compaction for analog integrated circuits
TLDR
A novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality is described.Abstract:Â
The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.read more
Citations
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Journal ArticleDOI
Automation of IC layout with analog constraints
TL;DR: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented, guaranteeing that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment.
Proceedings ArticleDOI
Generalized constraint generation for analog circuit design
TL;DR: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits.
Journal ArticleDOI
Optimum CMOS stack generation with analog constraints
E. Malavasi,D. Pandini +1 more
TL;DR: An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described, and the quality of results is comparable to that of hand-made circuits.
Proceedings ArticleDOI
Layout tools for analog ICs and mixed-signal SoCs: a survey
Rob A. Rutenbar,John M. Cohn +1 more
TL;DR: This short survey enumerates briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.
Proceedings ArticleDOI
A novel analog module generator environment
TL;DR: A novel analog module generator environment for the automatic layout development of analog circuits and a novel procedural layout description language that drastically eases the creation of analog modules is described.
References
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Proceedings ArticleDOI
Constraint generation for routing analog circuits
TL;DR: It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.
Journal ArticleDOI
Constraint-based channel routing for analog and mixed analog/digital circuits
TL;DR: It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans, so a technique to achieve almost perfect mirror symmetry is presented for such pairs of nets.
Proceedings ArticleDOI
An efficient algorithm for layout compaction problem with symmetry constraints
TL;DR: An efficient algorithm is presented for the symbolic layout compaction problem with symmetry constraints that uses both the graph-based technique and the linear programming technique, and takes advantage of the high speed of the former and the generality of the latter.
Proceedings ArticleDOI
A Constraint-driven Placement Methodology For Analog Integrated Circuits
TL;DR: A new constraint-driven methodology for the placeinent of analog IC's is described, where electrical performance specifications are automatically translated into constraints on the layout parasitics and these constraints and the seiisiitivity iiiforinatioii of the circuit are used to control a Simulated Annealingbased placement algorithm.
Proceedings ArticleDOI
A routing methodology for analog integrated circuits
TL;DR: A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described, and sensitivities of performance to parasitics are computed, and a set of bounding constraints for Parasitics is determined.