Proceedings ArticleDOI
Performance-driven compaction for analog integrated circuits
TLDR
A novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality is described.Abstract:
The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.read more
Citations
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Journal ArticleDOI
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow
Haitham Eissa,Rami F. Salem,Ahmed Arafa,Sherif Hany,Abdelrahman ElMously,Mohamed Dessouky,D.G. Nairn,Mohab Anis +7 more
TL;DR: This paper presents a complete e-DFM solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) within an analog circuit design that are caused by different process variations.
Patent
Parameter Matching Hotspot Detection
TL;DR: In this paper, a technique for detecting hotspots using parameter matching is described. Butterworth et al. used the parameter matching technique to detect hotspots in an electronic circuit design.
Proceedings ArticleDOI
Automatic generation of transistor stacks for CMOS analog layout
TL;DR: A layout-driven approach to the design of analog cells is described and the choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function accounting for parasitic control and area optimization.
Proceedings ArticleDOI
Multi-SP: a representation with united rectangles for analog placement and routing
TL;DR: A common data-structure to the placement and multilayer routing, where devices and wires are represented by united rectangles, called multi-layer sequence-pair (multi-SP), which enables us to manage diversified methodologies such as device sizing and technology migration.
Generalized Constraint Generat ion for Analog Circuit Design
TL;DR: In this article, a general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits.
References
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Book
Combinatorial Algorithms for Integrated Circuit Layout
TL;DR: This paper will concern you to try reading combinatorial algorithms for integrated circuit layout as one of the reading material to finish quickly.
Journal ArticleDOI
KOAN/ANAGRAM II: new tools for device-level analog placement and routing
TL;DR: KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators.
KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing
TL;DR: In this article, the authors describe a new tool for device-level analog placement and routing called KOAN and ANAGRAM II, which uses general algorithmic techniques to find critical devicelevel layout optimizations rather than relying on a large library of fixed-topology module generators.
Book
A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits
Henry Chang,A. Sangiovanlli-Vincentelli,F. Balarin,Edoardo Charbon,U. Choudhury,G. Jusuf,E. Liu,E. Malavasi,R. Neff,Paul R. Gray +9 more
TL;DR: A top-down, constraint-driven design methodology for analog integrated circuits and some of the tools that support this methodology are described, including behavioral simulation tools, tools for physical assembly, and module generators.