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Power Integrity Modeling and Design for Semiconductors and Systems

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TLDR
This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Abstract
The First Comprehensive, Example-Rich Guide to Power Integrity ModelingProfessionals such as signal integrity engineers, package designers, and system architects need to thoroughly understand signal and power integrity issues in order to successfully design packages and boards for high speed systems Now, for the first time, there's a complete guide to power integrity modeling: everything you need to know, from the basics through the state of the artUsing realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noiseThe authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applicationsThe authors Introduce power delivery network components, analysis, high-frequency measurement, and modeling requirements Thoroughly explain modeling of power/ground planes, including plane behavior, lumped modeling, distributed circuit-based approaches, and much more Offer in-depth coverage of simultaneous switching noise, including modeling for return currents using time- and frequency-domain analysis Introduce several leading time-domain simulation methods, such as macromodeling, and discuss their advantages and disadvantages Present the application of the modeling methods on several advanced case studies that include high-speed servers, high-speed differential signaling, chip package analysis, materials characterization, embedded decoupling capacitors, and electromagnetic bandgap structures This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists It will also be valuable to developers building software that helps to analyze high-speed systems

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Proceedings ArticleDOI

Electrical characteristics of build-up substrates using new via structures

TL;DR: In this paper, the authors investigated how the BU via structures affect the power supply path, and discussed the design constraints of the via structures in the build-up layers, which significantly reduced the resistance and inductance of the PTH in the substrate, while yielding good connectivity and productivity.
Proceedings ArticleDOI

The impact of the planes parameters on the noise of a power distribution network

TL;DR: In this article, the magnitude of the parallel impedance is determined to make sure that the voltage drop does not exceed expectations, so this voltage drop that the current switching generates on printed circuit board power planes is becoming an increasingly important problem in high frequency designs.

Collaborative Symmetricity Exploitation for Offline Learning of Hardware Design Solver

TL;DR: In this article , a collaborative symmetricity exploitation (CSE) framework is proposed to train a solver for the decoupling capacitor placement problem (DPP), one of the significant hardware design problems.
Proceedings ArticleDOI

Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO

TL;DR: Measurement results of on-chip noise on power and ground rings for I/O cells in a simple test structure fabricated in 90nm process and measured timings of an output signal from chip to PCB board are presented.
Proceedings ArticleDOI

Effect of electromagnetic band-gap depredation by plating through hold in packaging application

TL;DR: In this special topic, some well know electromagnetic band-gap (EBG) structures are performed on FR4 2 layer substrate in 40×40mm size, and depredate by plating through via (PTH) to simulate effect reducing of EBG structures applied in SiP to find broadband power integrity solutions.
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