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Power Integrity Modeling and Design for Semiconductors and Systems

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TLDR
This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Abstract
The First Comprehensive, Example-Rich Guide to Power Integrity ModelingProfessionals such as signal integrity engineers, package designers, and system architects need to thoroughly understand signal and power integrity issues in order to successfully design packages and boards for high speed systems Now, for the first time, there's a complete guide to power integrity modeling: everything you need to know, from the basics through the state of the artUsing realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noiseThe authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applicationsThe authors Introduce power delivery network components, analysis, high-frequency measurement, and modeling requirements Thoroughly explain modeling of power/ground planes, including plane behavior, lumped modeling, distributed circuit-based approaches, and much more Offer in-depth coverage of simultaneous switching noise, including modeling for return currents using time- and frequency-domain analysis Introduce several leading time-domain simulation methods, such as macromodeling, and discuss their advantages and disadvantages Present the application of the modeling methods on several advanced case studies that include high-speed servers, high-speed differential signaling, chip package analysis, materials characterization, embedded decoupling capacitors, and electromagnetic bandgap structures This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists It will also be valuable to developers building software that helps to analyze high-speed systems

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Proceedings ArticleDOI

Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures

TL;DR: It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region and reduction effect of power supply noise and the impedance of PDN at each circuit block were evaluated based on chip-package-board co-design.
Proceedings ArticleDOI

Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design

TL;DR: This paper presents the electrical design and modeling of a new TSV type, called metal semiconductor (MES) TSV, in terms of its capability to carry high frequency signals and reduce cross talk, and proposes to use MES TSVs especially for ground TSVs.
Journal ArticleDOI

Physics-Based Circuit Modeling Methodology for System Power Integrity Analysis and Design

TL;DR: In this paper, a physics-based circuit modeling methodology for system-level power integrity (PI) analysis and design is presented, which is based on representing the current paths in the power distribution network (PDN) with appropriate circuits based on cavity model and plane-pair partial element equivalent circuit (PEEC).
Proceedings ArticleDOI

Macromodeling of complex power delivery networks for efficient transient simulation

TL;DR: In this paper, the authors use vector fitting to create a macromodel of a power delivery network by first calculating its frequency response, which is much smaller than the original model, hence the efficiency is greatly improved.

Evaluation of power supply noise reduction by implementing on-chip capacitance

TL;DR: In this article, a test chip with on-chip decoupling capacitance and noise generating circuits has been reported using CMOS 0.18 μm process, and the effects of onchip capacitance on noise reduction ware evaluated by measuring the test chip as well as by using power supply noise analysis tool.
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