Proceedings ArticleDOI
Probabilistic Error Modeling for Two-part Segmented Approximate Adders
D. Celia,Vinita Vasudevan,Nitin Chandrachoodan +2 more
- pp 1-5
TLDR
This paper model the error of various two-part segmented approximate adders using probabilistic analysis and derive expressions for some basic error metrics used in literature and compares the results obtained using these expressions for various error metrics with those using Monte Carlo simulations for different input distributions.Abstract:
Approximate adders are used in applications that are error tolerant to save on power and area. We consider the class of two-part segmented approximate adders, where the upper part of the sum is computed accurately and the lower part of the sum is approximated. In this paper, we model the error of various two-part segmented approximate adders using probabilistic analysis and derive expressions for some basic error metrics used in literature. We compare the results obtained using our expressions for various error metrics with those using Monte Carlo simulations for different input distributions. Further, in an image addition application, we use our expression derived for mean square error and show that it predicts the PSNR correctly.read more
Citations
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Journal ArticleDOI
Small Constant Mean-Error Imprecise Adder/Multiplier for Efficient VLSI Implementation of MAC-Based Applications
TL;DR: Efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing.
Journal ArticleDOI
An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures
TL;DR: Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.
Journal ArticleDOI
A power and area efficient approximate carry skip adder for error resilient applications
TL;DR: This paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations.
Posted Content
Optimization of DSP Applications Using Parameterized Error Models for Low Power Approximate Adders
TL;DR: A significant improvement of accuracy in the prediction of the noise power of DSP systems containing approximate adders and parameterized error models are derived that can be used within any optimization framework in order to optimize the number of approximate bits.
Journal ArticleDOI
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing
Bo Liu,Ziyue Wang,Xuetao Wang,Ren-cheng Zhang,Anfeng Xue,Qi Shen,Na Xie,Yu Gong,Zhen Wang,Jun Yang,Hao Cai +10 more
TL;DR: An efficient BCNN deployment method is proposed, including a quality-circuit co-design method for approximate adder generation, aquality-aware intercompensation approach for addition tree, and a computing quality involved retraining approach forBCNN deployment.
References
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Journal ArticleDOI
Probabilistic Error Modeling for Approximate Adders
TL;DR: A generic methodology for analytical modeling of probability of occurrence of error and the Probability Mass Function of error value in a selected class of approximate adders is presented, which can serve as performance metrics for the comparative analysis of various adders and their configurations.
Proceedings ArticleDOI
A methodology for energy-quality tradeoff using imprecise hardware
TL;DR: Imprecise Hardware with design-time structural parameters can achieve orthogonal energy-quality tradeoffs and a simulation-free error estimation technique is proposed to rapidly and accurately estimate the impact of IHW on output quality.
Proceedings ArticleDOI
Approximate computing: An integrated hardware approach
TL;DR: This work describes an integrated approach to approximate computing in hardware that consists of an automatic resilience characterization framework that allows the designer to quantitatively evaluate the intrinsic resilience of an application, and to quickly assess the potential of various approximate computing techniques.