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Proceedings ArticleDOI

PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs

Li Zhou, +1 more
- pp 1-8
TLDR
The performance on synthetic and real traffic (PARSEC, Splash2) for 64-cores indicate that the proposed bandwidth scaling technique can reduce optical power by about 60% with at most 11% throughput penalty.
Abstract
Optical interconnect is a disruptive technology solution that can overcome the power and bandwidth limitations of traditional electrical Networks-on-Chip (NoCs). However, the static power dissipated in the external laser may limit the performance of future optical NoCs by dominating the stringent network power budget. From the analysis of real benchmarks for multicores, it is observed that high static power is consumed due to the external laser even for low channel utilization. In this paper, we propose PROBE: Prediction-based Optical Bandwidth Scaling for Energy-efficient NoCs by exploiting the latency/bandwidth trade-off to reduce the static power consumption by increasing the average channel utilization. With a lightweight prediction technique, we scale the bandwidth adaptively to the changing traffic demands while maintaining reasonable performance. The performance on synthetic and real traffic (PARSEC, Splash2) for 64-cores indicate that our proposed bandwidth scaling technique can reduce optical power by about 60% with at most 11% throughput penalty.

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Citations
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Journal ArticleDOI

A Survey on Optical Network-on-Chip Architectures

TL;DR: An exhaustive review of recently proposed ONoC architectures, which discusses their strengths and weaknesses, and discusses recent research efforts in key enabling technologies, which are essential to enable a widespread commercial adoption of ONoCs in the future.
Journal ArticleDOI

LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip

TL;DR: A novel nano-photonic NoC (PNoC) architecture, LumiNOC, optimized for high performance and power-efficiency, which partitions the network into subnets for better efficiency and reduces latencies against electrical 2-D mesh NoCs on the PARSEC shared-memory, multithreaded benchmark suite.
Proceedings ArticleDOI

LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures

TL;DR: A novel nano-photonic NoC (PNoC) architecture, LumiNOC, optimized for high performance and power-efficiency, which partitions the network into subnets for better efficiency and reduces latencies on the PARSEC shared-memory, multithreaded benchmark suite.
Journal ArticleDOI

A Survey of On-Chip Optical Interconnects

TL;DR: A survey of on-chip optical technologies covering the basic physics underlying the operation of optical technologies, optical devices, popular architectures, power reduction techniques, and applications is provided.
Proceedings ArticleDOI

Sharing and placement of on-chip laser sources in silicon-photonic NoCs

TL;DR: This paper uses a 3D stacked system that integrates a manycore chip with the optical devices and laser sources to explore the design space for laser source sharing and placement to minimize laser power by simultaneously considering the network bandwidth requirements, thermal constraints, and physical layout constraints.
References
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Proceedings ArticleDOI

The SPLASH-2 programs: characterization and methodological considerations

TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Proceedings ArticleDOI

The PARSEC benchmark suite: characterization and architectural implications

TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Book

Principles and Practices of Interconnection Networks

TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
Journal ArticleDOI

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

TL;DR: The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers as mentioned in this paper, which includes a set of timing simulator modules for modeling the timing of the memory system and microprocessors.

Multifacets General Execution-Driven Multiprocessor Simulator (GEMS) Toolset

M. M. Martin
TL;DR: The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers and has released a set of timing simulator modules for modeling the timing of the memory system and microprocessors.
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