Journal ArticleDOI
Corona: System Implications of Emerging Nanophotonic Technology
Dana M. Vantrease,Robert Schreiber,Matteo Monchiero,Moray McLaren,Norman P. Jouppi,Marco Fiorentino,Al Davis,Nathan Binkert,Raymond G. Beausoleil,Jung Ho Ahn +9 more
- Vol. 36, Iss: 3, pp 153-164
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TLDR
This work believes that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously reducing power.Abstract:
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on-stack bandwidth requirements at acceptable power levels. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously reducing power.read more
Citations
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Journal ArticleDOI
Single-chip microprocessor that communicates directly using light
Chen Sun,Chen Sun,Mark T. Wade,Yunsup Lee,Jason S. Orcutt,Jason S. Orcutt,Luca Alloatti,Michael Georgas,Andrew Waterman,Jeffrey M. Shainline,Jeffrey M. Shainline,Rimas Avizienis,Sen Lin,Benjamin Moss,Rajesh Kumar,Fabio Pavanello,Amir H. Atabaki,Henry Cook,Albert Ou,Jonathan Leu,Yu-Hsin Chen,Krste Asanovic,Rajeev J. Ram,Milos A. Popovic,Vladimir Stojanovic +24 more
TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Proceedings ArticleDOI
Helios: a hybrid electrical/optical switch architecture for modular data centers
Nathan Farrington,George Porter,Sivasankar Radhakrishnan,Hamid Hajabdolali Bazzaz,Vikram Subramanya,Yeshaiahu Fainman,George C. Papen,Amin Vahdat +7 more
TL;DR: This work presents Helios, a hybrid electrical/optical switch architecture that can deliver significant reductions in the number of switching elements, cabling, cost, and power consumption relative to recently proposed data center network architectures.
Proceedings ArticleDOI
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
Chen Sun,Chia-Hsin Owen Chen,George Kurian,Lan Wei,Jason Miller,Anant Agarwal,Li-Shiuan Peh,Vladimir Stojanovic +7 more
TL;DR: DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks, is presented and the results show the implications of different technology scenarios and the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
Proceedings ArticleDOI
Firefly: illuminating future network-on-chip with nanophotonics
TL;DR: Firefly is a hybrid, hierarchical network architecture that consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotinics is used only for global communication to realize an efficient on-chip network.
Journal ArticleDOI
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
Amlan Ganguly,Kevin Chang,Sujay Deb,Partha Pratim Pande,Benjamin J. Belzer,Christof Teuscher +5 more
TL;DR: It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude.
References
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Proceedings ArticleDOI
The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Journal ArticleDOI
Micrometre-scale silicon electro-optic modulator
TL;DR: Electro-optic modulators are one of the most critical components in optoelectronic integration, and decreasing their size may enable novel chip architectures, and here a high-speed electro-optical modulator in compact silicon structures is experimentally demonstrated.
The Landscape of Parallel Computing Research: A View from Berkeley
Krste Asanovic,Ras Bodik,Bryan Catanzaro,Joseph Gebis,Parry Husbands,Kurt Keutzer,David A. Patterson,William Plishker,John Shalf,Samuel Williams,Katherine Yelick +10 more
TL;DR: The parallel landscape is frame with seven questions, and the following are recommended to explore the design space rapidly: • The overarching goal should be to make it easy to write programs that execute efficiently on highly parallel computing systems • The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS each development dollar.
Journal ArticleDOI
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
TL;DR: In this article, a deadlock-free routing algorithm for arbitrary interconnection networks using the concept of virtual channels is presented, where the necessary and sufficient condition for deadlock free routing is the absence of cycles in a channel dependency graph.
Book
Deadlock-free message routing in multiprocessor interconnection networks
TL;DR: A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels, which is used to develop deadlocked routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.