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Journal ArticleDOI

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to $(8n+1)$ -bit

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TLDR
Methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8n+1)-bit are proposed, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.
Abstract
In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2n,2n-1,2n+1,2n-2(n+1)/2+1,2n+2(n+1)/2+1} , with an equivalent 5n -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the 2n+1+1 or 2n-1+1 moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8n+1)-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.

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Citations
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Journal ArticleDOI

Residue-to-binary conversion for general moduli sets based on approximate Chinese remainder theorem

TL;DR: An improved approximate Chinese remainder theorem (CRT) is presented with the aim of performing efficient residue-to-binary conversion for general RNS moduli sets and a method is proposed to substitute fractional calculations by similar computations based on integer numbers to have a hardware amenable algorithm.
Journal ArticleDOI

Method to Design General RNS Reverse Converters for Extended Moduli Sets

TL;DR: The experimental results suggest that the proposed moduli set extensions allow for larger and more balanced moduli sets, in comparison with the state of the art, resulting in an improvement of the overall RNS performance at the cost of a slower reverse conversion operation.
Journal ArticleDOI

A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set

TL;DR: The paper proposes an efficient residue-to-binary converter along with a converter-based sign detector for this extended five moduli set and presents a residue- to-residue transformer that enables the five-moduli set to utilize components that are (or will be) designed for the three-modulus set such as sign detectors.
Journal ArticleDOI

A Residue-to-Binary Converter for the Extended Four-Moduli Set $\{2^{n}-1, 2^{n}+1, 2^{2n}+1, 2^{2n+p}\} $

TL;DR: The main contribution of this brief is reducing the requirements of the proposed CSA network, which has impacted the area, delay, power and energy.
Journal ArticleDOI

Arithmetic-Based Binary-to-RNS Converter Modulo ${\{2^{n}{\pm}k\}}$ for $jn$ -bit Dynamic Range

TL;DR: The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art.
References
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A Suggestion for a Fast Multiplier

TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI

A Suggestion for a Fast Multiplier

TL;DR: The author develops an adder tree to sum this set when t= 1 the maximum number of regions intersections of n t-flats and shows that a tree will be dependent on both t and n.
Book

Residue Number Systems: Theory and Implementation

TL;DR: This book provides an up-to-date account of RNSs and arithmetic and covers the underlying mathematical concepts of R NSs; the conversion between conventional number systems and RNSS; the implementation of arithmetic operations; various related applications are introduced.
Proceedings ArticleDOI

Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication

TL;DR: It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition, and a high-performance modulo multiplier-adder for the IDEA block cipher is presented.
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