Patent
Semiconductor device having a gate electrode in a grove and a diffused region under the grove
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TLDR
In this article, a power MOSFET with a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film.Abstract:
A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.read more
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Patent
Power semiconductor devices and methods of manufacture
Ashok Challa,Alan Elbanhawy,Thomas E. Grebs,Nathan Kraft,Dean E. Probst,Rodney S. Ridley,Steven Sapp,Qi Wang,Chongman Yun,J.G. Lee,Peter H. Wilson,Joseph A. Yedinak,J.Y. Jung,Hocheol Jang,Babak S. Sani,Richard Stokes,Gary M. Dolny,John Mytych,Becky Losee,Adam Selsley,Robert Herrick,James J. Murphy,Gordon K. Madson,Bruce D. Marchant,Christopher L. Rexer,Christopher Boguslaw Kocon,Debra S. Woolsey +26 more
TL;DR: In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.
Patent
Superjunction Structures for Power Devices and Methods of Manufacture
Joseph A. Yedinak,Christopher L. Rexer,Mark L. Rinehimer,Praveen Muraleedharan Shenoy,Jaegil Lee,Hamza Yilmaz,Chong-Man Yun,Dwayne S. Reichl,James Pan,Rodney S. Ridley,Harold Heidenreich +10 more
TL;DR: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type as discussed by the authors, and each of the plurality of pillars of second conductivities type further includes an implant portion filled with semiconductor material.
Patent
High density trench DMOS transistor with trench bottom implant
TL;DR: In this paper, a trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom by providing a doped trench and extending into the surrounding drift region.
Patent
Methods of forming power semiconductor devices having tapered trench-based insulating regions therein
TL;DR: In this paper, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness T ins (y) in a range between about 0.5 and 1.5 times T ideal (y).
Patent
Trench-based power semiconductor devices with increased breakdown voltage characteristics
Joseph A. Yedinak,Ashok Challa +1 more
TL;DR: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed in this article, where the authors present a comparison of different types of power semiconductors with different benefits.
References
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Patent
Vertical insulated gate transistor and method of manufacture
TL;DR: In this paper, a vertical insulated gate transistor such as a UMOSFET is manufactured, where a source region of first conductivity type is formed on the bottom surface of a substrate.
Patent
Trench gate structure with thick bottom oxide
TL;DR: Improved trench gate field effect devices are provided by forming a thick oxide at the bottom of the trench as discussed by the authors, which may be preferably formed by ion implantation into the bottom layer of a trench.
Patent
Method for obtaining regions of dielectrically isolated single crystal silicon
TL;DR: In this article, a method of forming single crystal islands by epitaxial growth from a monocrystalline substrate was proposed, where a or other suitable low index surface was preferentially etched to void an inverted pyramid section with or other low index sidewalls.
Patent
Method for setting the threshold voltage of a power mosfet
TL;DR: In this article, a V groove with a flat bottom is anisotropically etched through openings in the oxide layer, which is used to set the threshold voltage of enhancement mode power MOSFETS, without compromising the breakdown voltage.
Patent
V-Mos field effect transistor
TL;DR: In this article, a field effect transistor of the V-MOS type has a layer-shaped first region (3), a subjacent second region (2, 1) of the second conductivity type and an island-shaped zone (4), which is covered with an insulating layer (6) and a gate electrode layer (8).