Patent
Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
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TLDR
In this paper, a gate dielectric layer is used to cover the exposed top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gated layer and extending through two sidewall thereof to reach the isolation material.Abstract:
The present disclosure provides a system and method for forming device on an insulator material. First, a semiconductor depletion material is formed with a predetermined height and width overlying a predetermined portion of the substrate to from an active region. An isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region. A gate dielectric layer is deposited for covering the exposed the top and two sidewalls of the top portion of the active region, and at least one gate electrode is then formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material.read more
Citations
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Patent
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
TL;DR: In this article, a planar SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer, followed by a partially-depleted SOI (PD-SOI) layer.
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References
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Patent
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu,Tsu-Jae King,Vivek Subramanian,Leland Chang,Xuejue Huang,Yang-Kyu Choi,Jakub Tadeusz Kedzierski,Nick Lindert,Jeffrey Bokor,Wen-Chin Lee +9 more
TL;DR: In this article, a planar MOSFET is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layers as a fin.
Patent
Fin fet devices from bulk semiconductor and method for forming
TL;DR: In this article, a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity.
Journal ArticleDOI
SOI technology for the GHz era
TL;DR: The reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond are described, which is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.
Proceedings ArticleDOI
A 50 nm depleted-substrate CMOS transistor (DST)
R. Chau,Jack Portland Kavalieros,Brian S. Doyle,Anand Portland Murthy,N. Paulsen,D. Lionberger,Douglas W. Barlage,R. Arghavani,B. Roberds,Mark Beaverton Doczy +9 more
TL;DR: In this article, a depleted-substrate transistor (DST) was proposed for thin Si transistors with raised source/drain, which achieved a significant performance gain over bulk Si without the floating body effect.
Patent
Process for making high performance silicon-on-insulator transistor with body node to source node connection
Terence G. W. Blake,Hsindao Lu +1 more
TL;DR: In this paper, a process for making a silicon-on-insulator MOS transistor is described, which includes forming an implanted region on the source side of the gate electrode for making contact to the body node.
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